--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.39
--  \   \         Application: netgen
--  /   /         Filename: I2CmasterDemo2_timesim.vhd
-- /___/   /\     Timestamp: Sat Jan 23 01:26:31 2010
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 4 -pcf I2CmasterDemo2.pcf -rpw 100 -tpw 0 -ar Structure -tm I2CmasterDemo2 -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim I2CmasterDemo2.ncd I2CmasterDemo2_timesim.vhd 
-- Device	: 3s250epq208-4 (PRODUCTION 1.27 2008-01-09)
-- Input file	: I2CmasterDemo2.ncd
-- Output file	: C:\Documents and Settings\sxs5464\Desktop\RapidFPGA\code\Xilinx Projects\ImagerController\netgen\par\I2CmasterDemo2_timesim.vhd
-- # of Entities	: 1
-- Design Name	: I2CmasterDemo2
-- Xilinx	: C:\Xilinx\10.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity I2CmasterDemo2 is
  port (
    I2C_Data : inout STD_LOGIC; 
    I2C_Clk : out STD_LOGIC; 
    FPGA_Clk : in STD_LOGIC := 'X'; 
    SW : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end I2CmasterDemo2;

architecture Structure of I2CmasterDemo2 is
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_1_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_3_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_5_Q : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_7_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_1_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_3_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_5_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_7_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_9_Q : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_11_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q : STD_LOGIC; 
  signal N45_0 : STD_LOGIC; 
  signal FPGA_Clk_BUFGP : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq0000_0 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_1_Q : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_3_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q : STD_LOGIC; 
  signal UUT_in_i2c_2430 : STD_LOGIC; 
  signal UUT_Dir_2431 : STD_LOGIC; 
  signal out_i2c : STD_LOGIC; 
  signal SW_0_IBUF_2433 : STD_LOGIC; 
  signal SW_1_IBUF_2434 : STD_LOGIC; 
  signal SW_2_IBUF_2435 : STD_LOGIC; 
  signal UUT_out_i2cclk_2438 : STD_LOGIC; 
  signal UUT_nstate_FFd1_2439 : STD_LOGIC; 
  signal UUT_nstate_FFd3_2440 : STD_LOGIC; 
  signal UUT_nstate_FFd2_2441 : STD_LOGIC; 
  signal UUT_nstate_FFd4_2442 : STD_LOGIC; 
  signal UUT_Dir_mux000025 : STD_LOGIC; 
  signal UUT_Dir_mux0000164 : STD_LOGIC; 
  signal UUT_ack_count_cmp_eq0000_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0007 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_2447 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0001_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_1175_0 : STD_LOGIC; 
  signal UUT_N40 : STD_LOGIC; 
  signal N53 : STD_LOGIC; 
  signal N54 : STD_LOGIC; 
  signal UUT_shiftReg_and0000_0 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0002_0 : STD_LOGIC; 
  signal UUT_Madd_counter_addsub0000_cy_2_0 : STD_LOGIC; 
  signal UUT_N62 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0012_0 : STD_LOGIC; 
  signal CLK_sI2C_Clk_2470 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0014 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_7_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_28_2476 : STD_LOGIC; 
  signal N64_0 : STD_LOGIC; 
  signal UUT_delay_count_or0001 : STD_LOGIC; 
  signal UUT_Dir_mux000062_0 : STD_LOGIC; 
  signal UUT_N33_0 : STD_LOGIC; 
  signal UUT_Dir_mux000057_0 : STD_LOGIC; 
  signal UUT_Dir_mux000083_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_1137_0 : STD_LOGIC; 
  signal N39_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_11104_SW2_O : STD_LOGIC; 
  signal N40_0 : STD_LOGIC; 
  signal N36_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_11104_SW1_O : STD_LOGIC; 
  signal N37_0 : STD_LOGIC; 
  signal UUT_N44 : STD_LOGIC; 
  signal UUT_N38 : STD_LOGIC; 
  signal N111_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00003_SW0_O : STD_LOGIC; 
  signal UUT_N32_0 : STD_LOGIC; 
  signal UUT_N100 : STD_LOGIC; 
  signal N16_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux000078 : STD_LOGIC; 
  signal UUT_N2116_0 : STD_LOGIC; 
  signal UUT_N2119_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0015 : STD_LOGIC; 
  signal UUT_ack_count_and0023 : STD_LOGIC; 
  signal UUT_N2140_0 : STD_LOGIC; 
  signal UUT_N2181_SW0_O : STD_LOGIC; 
  signal UUT_N2181_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000227_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000205_O : STD_LOGIC; 
  signal UUT_Dir_mux0000178_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000203_0 : STD_LOGIC; 
  signal UUT_Dir_mux0000230_0 : STD_LOGIC; 
  signal UUT_N1111 : STD_LOGIC; 
  signal N25 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq00031_SW1_O : STD_LOGIC; 
  signal UUT_N37 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_45_SW0_O : STD_LOGIC; 
  signal N126_0 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_45_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_1115_0 : STD_LOGIC; 
  signal N117_0 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In62_2521 : STD_LOGIC; 
  signal UUT_N41_0 : STD_LOGIC; 
  signal UUT_shiftReg_or00002_SW0_O : STD_LOGIC; 
  signal UUT_N79_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00009_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000018_O : STD_LOGIC; 
  signal UUT_N22 : STD_LOGIC; 
  signal UUT_N20 : STD_LOGIC; 
  signal UUT_N21_0 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In1_0 : STD_LOGIC; 
  signal UUT_in_i2c_and0000_0 : STD_LOGIC; 
  signal UUT_in_i2c_cmp_eq0000 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000064_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000080_0 : STD_LOGIC; 
  signal UUT_N2170_0 : STD_LOGIC; 
  signal UUT_N21130_O : STD_LOGIC; 
  signal N91_0 : STD_LOGIC; 
  signal UUT_N21151_0 : STD_LOGIC; 
  signal UUT_N217_O : STD_LOGIC; 
  signal UUT_Dir_mux000092_O : STD_LOGIC; 
  signal UUT_delay_count_or0000 : STD_LOGIC; 
  signal UUT_Dir_mux000035_2544 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_2545 : STD_LOGIC; 
  signal N21_0 : STD_LOGIC; 
  signal N73_0 : STD_LOGIC; 
  signal N31_0 : STD_LOGIC; 
  signal UUT_N0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_30_0 : STD_LOGIC; 
  signal UUT_N11 : STD_LOGIC; 
  signal UUT_N31 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_2553 : STD_LOGIC; 
  signal UUT_N26_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0006_0 : STD_LOGIC; 
  signal UUT_N46 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_8_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_2_0 : STD_LOGIC; 
  signal UUT_Dir_mux00012_SW0_O : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_68_O : STD_LOGIC; 
  signal N89_0 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_210_0 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_20_O : STD_LOGIC; 
  signal UUT_N16_0 : STD_LOGIC; 
  signal N97_0 : STD_LOGIC; 
  signal UUT_shiftReg_or000012_O : STD_LOGIC; 
  signal UUT_shiftReg_or000017_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_210_0 : STD_LOGIC; 
  signal N51_0 : STD_LOGIC; 
  signal UUT_N42 : STD_LOGIC; 
  signal UUT_Dir_mux0000122_2573 : STD_LOGIC; 
  signal UUT_N29_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_218_O : STD_LOGIC; 
  signal UUT_shiftReg_or0000 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_232_0 : STD_LOGIC; 
  signal UUT_shiftReg_or000032_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_316_0 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0011_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_39_2581 : STD_LOGIC; 
  signal UUT_N25_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_215_2583 : STD_LOGIC; 
  signal UUT_N15_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000218_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000227_0 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_SW1_O : STD_LOGIC; 
  signal N58_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000258_SW0_O : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000258_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_257_SW3_O : STD_LOGIC; 
  signal N67_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_3_0 : STD_LOGIC; 
  signal N19_0 : STD_LOGIC; 
  signal UUT_N112_0 : STD_LOGIC; 
  signal UUT_N101 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_257_SW1_O : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_SW0_O : STD_LOGIC; 
  signal UUT_N104_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_328_SW0_O : STD_LOGIC; 
  signal UUT_N106_0 : STD_LOGIC; 
  signal N77_0 : STD_LOGIC; 
  signal UUT_nstate_FFd1_In33_O : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0005_0 : STD_LOGIC; 
  signal N93_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000050_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000097_O : STD_LOGIC; 
  signal UUT_N107 : STD_LOGIC; 
  signal UUT_delay_count_and0000_0 : STD_LOGIC; 
  signal UUT_N17_0 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In59_0 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In28_O : STD_LOGIC; 
  signal UUT_in_i2c_mux000032_O : STD_LOGIC; 
  signal N113_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux000034_0 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_125_SW0_O : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_125_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000211_O : STD_LOGIC; 
  signal N95_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000131_O : STD_LOGIC; 
  signal UUT_in_i2c_mux0000144_0 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_145_O : STD_LOGIC; 
  signal UUT_N3_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux000093_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000122_O : STD_LOGIC; 
  signal UUT_in_i2c_mux0000158_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000190_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000266_O : STD_LOGIC; 
  signal UUT_in_i2c_mux0000275_0 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000210_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux000099_0 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0000_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000250_O : STD_LOGIC; 
  signal UUT_in_i2c_mux0000247_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000287_0 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000216_O : STD_LOGIC; 
  signal N99_0 : STD_LOGIC; 
  signal N18_0 : STD_LOGIC; 
  signal UUT_prevClk_2652 : STD_LOGIC; 
  signal N33_0 : STD_LOGIC; 
  signal N101_0 : STD_LOGIC; 
  signal UUT_N66_0 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq00007_0 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq000016_2666 : STD_LOGIC; 
  signal N120_0 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_2 : STD_LOGIC; 
  signal N128 : STD_LOGIC; 
  signal UUT_nstate_FFd2_In11_2670 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_XORF_2705 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_LOGIC_ONE_2704 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYINIT_2703 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYSELF_2694 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_XORG_2690 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYMUXG_2689 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_LOGIC_ZERO_2687 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_CYSELG_2678 : STD_LOGIC; 
  signal UUT_writeCount_share0000_0_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_XORF_2743 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYINIT_2742 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_XORG_2731 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYSELF_2729 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYMUXFAST_2728 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYAND_2727 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_FASTCARRY_2726 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYMUXG2_2725 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYMUXF2_2724 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_LOGIC_ZERO_2723 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_CYSELG_2714 : STD_LOGIC; 
  signal UUT_writeCount_share0000_2_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_XORF_2781 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYINIT_2780 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_XORG_2769 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYSELF_2767 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYMUXFAST_2766 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYAND_2765 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_FASTCARRY_2764 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYMUXG2_2763 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYMUXF2_2762 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_LOGIC_ZERO_2761 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_CYSELG_2752 : STD_LOGIC; 
  signal UUT_writeCount_share0000_4_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_XORF_2819 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYINIT_2818 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_XORG_2807 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYSELF_2805 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYMUXFAST_2804 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYAND_2803 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_FASTCARRY_2802 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYMUXG2_2801 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYMUXF2_2800 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_LOGIC_ZERO_2799 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_CYSELG_2790 : STD_LOGIC; 
  signal UUT_writeCount_share0000_6_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_XORF_2857 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYINIT_2856 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_XORG_2845 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYSELF_2843 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYMUXFAST_2842 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYAND_2841 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_FASTCARRY_2840 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYMUXG2_2839 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYMUXF2_2838 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_LOGIC_ZERO_2837 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_CYSELG_2828 : STD_LOGIC; 
  signal UUT_writeCount_share0000_8_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_XORF_2895 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYINIT_2894 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_XORG_2883 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYSELF_2881 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYMUXFAST_2880 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYAND_2879 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_FASTCARRY_2878 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYMUXG2_2877 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYMUXF2_2876 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_LOGIC_ZERO_2875 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_CYSELG_2866 : STD_LOGIC; 
  signal UUT_writeCount_share0000_10_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_XORF_3547 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYINIT_3546 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_XORG_3535 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_8_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYSELF_3533 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYMUXFAST_3532 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYAND_3531 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_FASTCARRY_3530 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYMUXG2_3529 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYMUXF2_3528 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_LOGIC_ZERO_3527 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_CYSELG_3518 : STD_LOGIC; 
  signal UUT_ack_count_share0000_8_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_XORF_3578 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_LOGIC_ZERO_3577 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_CYINIT_3576 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_CYSELF_3567 : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_10_XORG_3564 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_10_Q : STD_LOGIC; 
  signal UUT_ack_count_11_rt_3561 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3609 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT_3608 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF_3602 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_3601 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG_3599 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_0_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3597 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG_3589 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_3588 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_3634 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3633 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST_3632 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND_3631 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY_3630 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2_3629 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2_3628 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3627 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3619 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_3618 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT_3668 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF_3661 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG_3658 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3656 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG_3650 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3692 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST_3691 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND_3690 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY_3689 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2_3688 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2_3687 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3686 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3680 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3722 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST_3721 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND_3720 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY_3719 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2_3718 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2_3717 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3716 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3710 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYSELF_3752 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYMUXFAST_3751 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYAND_3750 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_FASTCARRY_3749 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYMUXG2_3748 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYMUXF2_3747 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3746 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0001_CYSELG_3740 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_XORF_3793 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_LOGIC_ONE_3792 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYINIT_3791 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYSELF_3782 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_XORG_3778 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYMUXG_3777 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_0_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_LOGIC_ZERO_3775 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_CYSELG_3766 : STD_LOGIC; 
  signal UUT_delay_count_share0000_0_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_XORF_3831 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYINIT_3830 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_XORG_3819 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_2_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYSELF_3817 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYMUXFAST_3816 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYAND_3815 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_FASTCARRY_3814 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYMUXG2_3813 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYMUXF2_3812 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_LOGIC_ZERO_3811 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_CYSELG_3802 : STD_LOGIC; 
  signal UUT_delay_count_share0000_2_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_XORF_3237 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYINIT_3236 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_XORG_3225 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYSELF_3223 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYMUXFAST_3222 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYAND_3221 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_FASTCARRY_3220 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYMUXG2_3219 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYMUXF2_3218 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_LOGIC_ZERO_3217 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_CYSELG_3208 : STD_LOGIC; 
  signal UUT_writeCount_share0000_28_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_30_XORF_3252 : STD_LOGIC; 
  signal UUT_writeCount_share0000_30_CYINIT_3251 : STD_LOGIC; 
  signal UUT_writeCount_30_rt_3249 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO_3283 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT_3282 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF_3273 : STD_LOGIC; 
  signal UUT_delay_count_2_rt_3272 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG_3270 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE_3268 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG_3260 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_3259 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3314 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_3306 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3305 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST_3304 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND_3303 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY_3302 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2_3301 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2_3300 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE_3299 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3290 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3345 : STD_LOGIC; 
  signal UUT_delay_count_8_rt_3336 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3335 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST_3334 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND_3333 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY_3332 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2_3331 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2_3330 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE_3329 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3323 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_3322 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE_3360 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT_3359 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF_3352 : STD_LOGIC; 
  signal UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_3351 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_XORF_3395 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_LOGIC_ONE_3394 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYINIT_3393 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYSELF_3384 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_XORG_3380 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYMUXG_3379 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_0_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_LOGIC_ZERO_3377 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_CYSELG_3368 : STD_LOGIC; 
  signal UUT_ack_count_share0000_0_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_XORF_3433 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYINIT_3432 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_XORG_3421 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_2_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYSELF_3419 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYMUXFAST_3418 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYAND_3417 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_FASTCARRY_3416 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYMUXG2_3415 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYMUXF2_3414 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_LOGIC_ZERO_3413 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_CYSELG_3404 : STD_LOGIC; 
  signal UUT_ack_count_share0000_2_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_XORF_3471 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYINIT_3470 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_XORG_3459 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_4_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYSELF_3457 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYMUXFAST_3456 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYAND_3455 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_FASTCARRY_3454 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYMUXG2_3453 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYMUXF2_3452 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_LOGIC_ZERO_3451 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_CYSELG_3442 : STD_LOGIC; 
  signal UUT_ack_count_share0000_4_G : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_XORF_3509 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYINIT_3508 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_F : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_XORG_3497 : STD_LOGIC; 
  signal UUT_Madd_ack_count_share0000_cy_6_Q : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYSELF_3495 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYMUXFAST_3494 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYAND_3493 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_FASTCARRY_3492 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYMUXG2_3491 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYMUXF2_3490 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_LOGIC_ZERO_3489 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_CYSELG_3480 : STD_LOGIC; 
  signal UUT_ack_count_share0000_6_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_XORF_2933 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYINIT_2932 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_XORG_2921 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYSELF_2919 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYMUXFAST_2918 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYAND_2917 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_FASTCARRY_2916 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYMUXG2_2915 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYMUXF2_2914 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_LOGIC_ZERO_2913 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_CYSELG_2904 : STD_LOGIC; 
  signal UUT_writeCount_share0000_12_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_XORF_2971 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYINIT_2970 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_XORG_2959 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYSELF_2957 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYMUXFAST_2956 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYAND_2955 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_FASTCARRY_2954 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYMUXG2_2953 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYMUXF2_2952 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_LOGIC_ZERO_2951 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_CYSELG_2942 : STD_LOGIC; 
  signal UUT_writeCount_share0000_14_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_XORF_3009 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYINIT_3008 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_XORG_2997 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYSELF_2995 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYMUXFAST_2994 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYAND_2993 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_FASTCARRY_2992 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYMUXG2_2991 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYMUXF2_2990 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_LOGIC_ZERO_2989 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_CYSELG_2980 : STD_LOGIC; 
  signal UUT_writeCount_share0000_16_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_XORF_3047 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYINIT_3046 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_XORG_3035 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYSELF_3033 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYMUXFAST_3032 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYAND_3031 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_FASTCARRY_3030 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYMUXG2_3029 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYMUXF2_3028 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_LOGIC_ZERO_3027 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_CYSELG_3018 : STD_LOGIC; 
  signal UUT_writeCount_share0000_18_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_XORF_3085 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYINIT_3084 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_XORG_3073 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYSELF_3071 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYMUXFAST_3070 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYAND_3069 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_FASTCARRY_3068 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYMUXG2_3067 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYMUXF2_3066 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_LOGIC_ZERO_3065 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_CYSELG_3056 : STD_LOGIC; 
  signal UUT_writeCount_share0000_20_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_XORF_3123 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYINIT_3122 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_XORG_3111 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYSELF_3109 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYMUXFAST_3108 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYAND_3107 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_FASTCARRY_3106 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYMUXG2_3105 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYMUXF2_3104 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_LOGIC_ZERO_3103 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_CYSELG_3094 : STD_LOGIC; 
  signal UUT_writeCount_share0000_22_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_XORF_3161 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYINIT_3160 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_XORG_3149 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYSELF_3147 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYMUXFAST_3146 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYAND_3145 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_FASTCARRY_3144 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYMUXG2_3143 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYMUXF2_3142 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_LOGIC_ZERO_3141 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_CYSELG_3132 : STD_LOGIC; 
  signal UUT_writeCount_share0000_24_G : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_XORF_3199 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYINIT_3198 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_F : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_XORG_3187 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYSELF_3185 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYMUXFAST_3184 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYAND_3183 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_FASTCARRY_3182 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYMUXG2_3181 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYMUXF2_3180 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_LOGIC_ZERO_3179 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_CYSELG_3170 : STD_LOGIC; 
  signal UUT_writeCount_share0000_26_G : STD_LOGIC; 
  signal CLK_clk_div_2_DXMUX_4239 : STD_LOGIC; 
  signal CLK_clk_div_2_XORF_4237 : STD_LOGIC; 
  signal CLK_clk_div_2_CYINIT_4236 : STD_LOGIC; 
  signal CLK_clk_div_2_F : STD_LOGIC; 
  signal CLK_clk_div_2_DYMUX_4222 : STD_LOGIC; 
  signal CLK_clk_div_2_XORG_4220 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_2_Q : STD_LOGIC; 
  signal CLK_clk_div_2_CYSELF_4218 : STD_LOGIC; 
  signal CLK_clk_div_2_CYMUXFAST_4217 : STD_LOGIC; 
  signal CLK_clk_div_2_CYAND_4216 : STD_LOGIC; 
  signal CLK_clk_div_2_FASTCARRY_4215 : STD_LOGIC; 
  signal CLK_clk_div_2_CYMUXG2_4214 : STD_LOGIC; 
  signal CLK_clk_div_2_CYMUXF2_4213 : STD_LOGIC; 
  signal CLK_clk_div_2_LOGIC_ZERO_4212 : STD_LOGIC; 
  signal CLK_clk_div_2_CYSELG_4203 : STD_LOGIC; 
  signal CLK_clk_div_2_G : STD_LOGIC; 
  signal CLK_clk_div_2_SRINV_4201 : STD_LOGIC; 
  signal CLK_clk_div_2_CLKINV_4200 : STD_LOGIC; 
  signal CLK_clk_div_4_DXMUX_4291 : STD_LOGIC; 
  signal CLK_clk_div_4_XORF_4289 : STD_LOGIC; 
  signal CLK_clk_div_4_CYINIT_4288 : STD_LOGIC; 
  signal CLK_clk_div_4_F : STD_LOGIC; 
  signal CLK_clk_div_4_DYMUX_4274 : STD_LOGIC; 
  signal CLK_clk_div_4_XORG_4272 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_4_Q : STD_LOGIC; 
  signal CLK_clk_div_4_CYSELF_4270 : STD_LOGIC; 
  signal CLK_clk_div_4_CYMUXFAST_4269 : STD_LOGIC; 
  signal CLK_clk_div_4_CYAND_4268 : STD_LOGIC; 
  signal CLK_clk_div_4_FASTCARRY_4267 : STD_LOGIC; 
  signal CLK_clk_div_4_CYMUXG2_4266 : STD_LOGIC; 
  signal CLK_clk_div_4_CYMUXF2_4265 : STD_LOGIC; 
  signal CLK_clk_div_4_LOGIC_ZERO_4264 : STD_LOGIC; 
  signal CLK_clk_div_4_CYSELG_4255 : STD_LOGIC; 
  signal CLK_clk_div_4_G : STD_LOGIC; 
  signal CLK_clk_div_4_SRINV_4253 : STD_LOGIC; 
  signal CLK_clk_div_4_CLKINV_4252 : STD_LOGIC; 
  signal CLK_clk_div_6_DXMUX_4336 : STD_LOGIC; 
  signal CLK_clk_div_6_XORF_4334 : STD_LOGIC; 
  signal CLK_clk_div_6_LOGIC_ZERO_4333 : STD_LOGIC; 
  signal CLK_clk_div_6_CYINIT_4332 : STD_LOGIC; 
  signal CLK_clk_div_6_CYSELF_4323 : STD_LOGIC; 
  signal CLK_clk_div_6_F : STD_LOGIC; 
  signal CLK_clk_div_6_DYMUX_4317 : STD_LOGIC; 
  signal CLK_clk_div_6_XORG_4315 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_6_Q : STD_LOGIC; 
  signal CLK_clk_div_7_rt_4312 : STD_LOGIC; 
  signal CLK_clk_div_6_SRINV_4304 : STD_LOGIC; 
  signal CLK_clk_div_6_CLKINV_4303 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO_4370 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT_4369 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF_4361 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_4360 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG_4358 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_0_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE_4356 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG_4347 : STD_LOGIC; 
  signal UUT_delay_count_4_rt : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4401 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_2_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4391 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST_4390 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND_4389 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY_4388 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2_4387 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2_4386 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE_4385 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4377 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4432 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_4_1 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4422 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST_4421 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND_4420 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY_4419 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2_4418 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2_4417 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE_4416 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4408 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_4407 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4456 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST_4455 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND_4454 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY_4453 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2_4452 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2_4451 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4450 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4441 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO_4492 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT_4491 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF_4484 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG_4481 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE_4479 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG_4471 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4523 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4513 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST_4512 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND_4511 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY_4510 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2_4509 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2_4508 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE_4507 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4498 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_3_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_XORF_3869 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYINIT_3868 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_XORG_3857 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_4_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYSELF_3855 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYMUXFAST_3854 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYAND_3853 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_FASTCARRY_3852 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYMUXG2_3851 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYMUXF2_3850 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_LOGIC_ZERO_3849 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_CYSELG_3840 : STD_LOGIC; 
  signal UUT_delay_count_share0000_4_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_XORF_3907 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYINIT_3906 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_XORG_3895 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_6_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYSELF_3893 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYMUXFAST_3892 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYAND_3891 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_FASTCARRY_3890 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYMUXG2_3889 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYMUXF2_3888 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_LOGIC_ZERO_3887 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_CYSELG_3878 : STD_LOGIC; 
  signal UUT_delay_count_share0000_6_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_XORF_3945 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYINIT_3944 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_XORG_3933 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_8_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYSELF_3931 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYMUXFAST_3930 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYAND_3929 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_FASTCARRY_3928 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYMUXG2_3927 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYMUXF2_3926 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_LOGIC_ZERO_3925 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_CYSELG_3916 : STD_LOGIC; 
  signal UUT_delay_count_share0000_8_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_XORF_3983 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYINIT_3982 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_XORG_3971 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_10_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYSELF_3969 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYMUXFAST_3968 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYAND_3967 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_FASTCARRY_3966 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYMUXG2_3965 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYMUXF2_3964 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_LOGIC_ZERO_3963 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_CYSELG_3954 : STD_LOGIC; 
  signal UUT_delay_count_share0000_10_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_XORF_4021 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYINIT_4020 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_XORG_4009 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_12_Q : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYSELF_4007 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYMUXFAST_4006 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYAND_4005 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_FASTCARRY_4004 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYMUXG2_4003 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYMUXF2_4002 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_LOGIC_ZERO_4001 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_CYSELG_3992 : STD_LOGIC; 
  signal UUT_delay_count_share0000_12_G : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_XORF_4052 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_LOGIC_ZERO_4051 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_CYINIT_4050 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_CYSELF_4041 : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_F : STD_LOGIC; 
  signal UUT_delay_count_share0000_14_XORG_4038 : STD_LOGIC; 
  signal UUT_Madd_delay_count_share0000_cy_14_Q : STD_LOGIC; 
  signal UUT_delay_count_15_rt_4035 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO_4083 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT_4082 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF_4073 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG_4070 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE_4068 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG_4060 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4114 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4104 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST_4103 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND_4102 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY_4101 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2_4100 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2_4099 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE_4098 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4091 : STD_LOGIC; 
  signal N45_LOGIC_ZERO_4141 : STD_LOGIC; 
  signal N45_CYINIT_4140 : STD_LOGIC; 
  signal N45_CYSELF_4134 : STD_LOGIC; 
  signal N45 : STD_LOGIC; 
  signal CLK_clk_div_0_DXMUX_4187 : STD_LOGIC; 
  signal CLK_clk_div_0_XORF_4185 : STD_LOGIC; 
  signal CLK_clk_div_0_LOGIC_ONE_4184 : STD_LOGIC; 
  signal CLK_clk_div_0_CYINIT_4183 : STD_LOGIC; 
  signal CLK_clk_div_0_CYSELF_4174 : STD_LOGIC; 
  signal CLK_clk_div_0_DYMUX_4167 : STD_LOGIC; 
  signal CLK_clk_div_0_XORG_4165 : STD_LOGIC; 
  signal CLK_clk_div_0_CYMUXG_4164 : STD_LOGIC; 
  signal CLK_Mcount_clk_div_cy_0_Q : STD_LOGIC; 
  signal CLK_clk_div_0_LOGIC_ZERO_4162 : STD_LOGIC; 
  signal CLK_clk_div_0_CYSELG_4153 : STD_LOGIC; 
  signal CLK_clk_div_0_G : STD_LOGIC; 
  signal CLK_clk_div_0_SRINV_4151 : STD_LOGIC; 
  signal CLK_clk_div_0_CLKINV_4150 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4547 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST_4546 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND_4545 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY_4544 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2_4543 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2_4542 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4541 : STD_LOGIC; 
  signal UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4534 : STD_LOGIC; 
  signal I2C_Data_O : STD_LOGIC; 
  signal I2C_Data_T : STD_LOGIC; 
  signal I2C_Data_INBUF : STD_LOGIC; 
  signal SW_0_INBUF : STD_LOGIC; 
  signal SW_1_INBUF : STD_LOGIC; 
  signal SW_2_INBUF : STD_LOGIC; 
  signal SW_3_INBUF : STD_LOGIC; 
  signal FPGA_Clk_INBUF : STD_LOGIC; 
  signal I2C_Clk_O : STD_LOGIC; 
  signal FPGA_Clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal FPGA_Clk_BUFGP_BUFG_I0_INV : STD_LOGIC; 
  signal UUT_Dir_mux000025_F5MUX_4641 : STD_LOGIC; 
  signal N147 : STD_LOGIC; 
  signal UUT_Dir_mux000025_BXINV_4634 : STD_LOGIC; 
  signal N146 : STD_LOGIC; 
  signal UUT_Dir_mux0000164_F5MUX_4666 : STD_LOGIC; 
  signal N137 : STD_LOGIC; 
  signal UUT_Dir_mux0000164_BXINV_4659 : STD_LOGIC; 
  signal N136 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_10_F5MUX_4691 : STD_LOGIC; 
  signal N149 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_10_BXINV_4684 : STD_LOGIC; 
  signal N148 : STD_LOGIC; 
  signal N53_F5MUX_4716 : STD_LOGIC; 
  signal N82 : STD_LOGIC; 
  signal N53_BXINV_4709 : STD_LOGIC; 
  signal N81 : STD_LOGIC; 
  signal N54_F5MUX_4741 : STD_LOGIC; 
  signal N84 : STD_LOGIC; 
  signal N54_BXINV_4732 : STD_LOGIC; 
  signal N83 : STD_LOGIC; 
  signal UUT_nstate_FFd3_DXMUX_4772 : STD_LOGIC; 
  signal UUT_nstate_FFd3_F5MUX_4770 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In311 : STD_LOGIC; 
  signal UUT_nstate_FFd3_BXINV_4763 : STD_LOGIC; 
  signal UUT_nstate_FFd3_G : STD_LOGIC; 
  signal UUT_nstate_FFd3_SRINV_4752 : STD_LOGIC; 
  signal UUT_nstate_FFd3_CLKINV_4751 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_8_F5MUX_4800 : STD_LOGIC; 
  signal N145 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_8_BXINV_4793 : STD_LOGIC; 
  signal N144 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_8_F5MUX_4825 : STD_LOGIC; 
  signal N143 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_8_BXINV_4818 : STD_LOGIC; 
  signal N142 : STD_LOGIC; 
  signal UUT_nstate_FFd2_DXMUX_4856 : STD_LOGIC; 
  signal UUT_nstate_FFd2_F5MUX_4854 : STD_LOGIC; 
  signal N153 : STD_LOGIC; 
  signal UUT_nstate_FFd2_BXINV_4847 : STD_LOGIC; 
  signal N152 : STD_LOGIC; 
  signal UUT_nstate_FFd2_SRINV_4840 : STD_LOGIC; 
  signal UUT_nstate_FFd2_CLKINV_4839 : STD_LOGIC; 
  signal UUT_counter_4_DXMUX_4888 : STD_LOGIC; 
  signal UUT_counter_4_F5MUX_4886 : STD_LOGIC; 
  signal N139 : STD_LOGIC; 
  signal UUT_counter_4_BXINV_4879 : STD_LOGIC; 
  signal N138 : STD_LOGIC; 
  signal UUT_counter_4_CLKINV_4872 : STD_LOGIC; 
  signal UUT_counter_3_DXMUX_4919 : STD_LOGIC; 
  signal UUT_counter_3_F5MUX_4917 : STD_LOGIC; 
  signal N133 : STD_LOGIC; 
  signal UUT_counter_3_BXINV_4910 : STD_LOGIC; 
  signal N132 : STD_LOGIC; 
  signal UUT_counter_3_CLKINV_4902 : STD_LOGIC; 
  signal UUT_counter_2_DXMUX_4950 : STD_LOGIC; 
  signal UUT_counter_2_F5MUX_4948 : STD_LOGIC; 
  signal N141 : STD_LOGIC; 
  signal UUT_counter_2_BXINV_4941 : STD_LOGIC; 
  signal N140 : STD_LOGIC; 
  signal UUT_counter_2_CLKINV_4934 : STD_LOGIC; 
  signal UUT_counter_1_DXMUX_4981 : STD_LOGIC; 
  signal UUT_counter_1_F5MUX_4979 : STD_LOGIC; 
  signal N135 : STD_LOGIC; 
  signal UUT_counter_1_BXINV_4971 : STD_LOGIC; 
  signal N134 : STD_LOGIC; 
  signal UUT_counter_1_CLKINV_4964 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In14_F5MUX_5008 : STD_LOGIC; 
  signal N151 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In14_BXINV_5001 : STD_LOGIC; 
  signal N150 : STD_LOGIC; 
  signal N64 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0014_pack_1 : STD_LOGIC; 
  signal UUT_Dir_mux000083_5055 : STD_LOGIC; 
  signal UUT_delay_count_or0001_pack_1 : STD_LOGIC; 
  signal UUT_pstate_4_DXMUX_5084 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_11104_SW2_O_pack_1 : STD_LOGIC; 
  signal UUT_pstate_4_CLKINV_5069 : STD_LOGIC; 
  signal UUT_pstate_3_DXMUX_5114 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_11104_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_pstate_3_CLKINV_5099 : STD_LOGIC; 
  signal N111 : STD_LOGIC; 
  signal UUT_N44_pack_1 : STD_LOGIC; 
  signal UUT_N32 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00003_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_cmp_eq0000_5187 : STD_LOGIC; 
  signal UUT_N100_pack_1 : STD_LOGIC; 
  signal UUT_N2116_5211 : STD_LOGIC; 
  signal UUT_in_i2c_mux000078_pack_1 : STD_LOGIC; 
  signal UUT_N2140_5235 : STD_LOGIC; 
  signal UUT_ack_count_and0023_pack_1 : STD_LOGIC; 
  signal UUT_N2181_5259 : STD_LOGIC; 
  signal UUT_N2181_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_Dir_mux0000230_5283 : STD_LOGIC; 
  signal UUT_Dir_mux0000205_O_pack_1 : STD_LOGIC; 
  signal UUT_Dir_mux0000178_5307 : STD_LOGIC; 
  signal UUT_N1111_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_and0000 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq00031_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_45_5355 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_45_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_210_5919 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_28_pack_1 : STD_LOGIC; 
  signal UUT_N26 : STD_LOGIC; 
  signal UUT_N42_pack_1 : STD_LOGIC; 
  signal UUT_N29 : STD_LOGIC; 
  signal UUT_Dir_mux0000122_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_232_5991 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_218_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_316_6015 : STD_LOGIC; 
  signal UUT_shiftReg_or0000_pack_1 : STD_LOGIC; 
  signal UUT_N25 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_39_pack_1 : STD_LOGIC; 
  signal UUT_N15 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_215_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000227_6087 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000218_O_pack_1 : STD_LOGIC; 
  signal N58 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000258_6135 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000258_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_5_DXMUX_6166 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_11 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_257_SW3_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_5_SRINV_6151 : STD_LOGIC; 
  signal UUT_shiftReg_5_CLKINV_6150 : STD_LOGIC; 
  signal N19 : STD_LOGIC; 
  signal UUT_delay_count_or0000_pack_1 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0001_6216 : STD_LOGIC; 
  signal UUT_in_i2c_cmp_eq0000_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_7_DXMUX_6247 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_7_10 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_257_SW1_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_7_SRINV_6231 : STD_LOGIC; 
  signal UUT_shiftReg_7_CLKINV_6230 : STD_LOGIC; 
  signal UUT_shiftReg_2_DXMUX_6280 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_1_6277 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_2_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_2_SRINV_6264 : STD_LOGIC; 
  signal UUT_shiftReg_2_CLKINV_6263 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_0_6306 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_328_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_N33 : STD_LOGIC; 
  signal N25_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd1_DXMUX_6361 : STD_LOGIC; 
  signal UUT_nstate_FFd1_In42 : STD_LOGIC; 
  signal UUT_nstate_FFd1_In33_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd1_SRINV_6345 : STD_LOGIC; 
  signal UUT_nstate_FFd1_CLKINV_6344 : STD_LOGIC; 
  signal N93 : STD_LOGIC; 
  signal UUT_N38_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_DXMUX_6418 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000131 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000097_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_SRINV_6402 : STD_LOGIC; 
  signal UUT_out_i2cclk_CLKINV_6401 : STD_LOGIC; 
  signal UUT_N17 : STD_LOGIC; 
  signal UUT_N107_pack_1 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_1115_5379 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0007_pack_1 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_1137_5403 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In62_pack_1 : STD_LOGIC; 
  signal UUT_N79 : STD_LOGIC; 
  signal UUT_shiftReg_or00002_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000030_5451 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000018_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_6_DXMUX_5480 : STD_LOGIC; 
  signal UUT_N20_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_6_CLKINV_5465 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000080_5505 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000064_O_pack_1 : STD_LOGIC; 
  signal UUT_N21151_5529 : STD_LOGIC; 
  signal UUT_N21130_O_pack_1 : STD_LOGIC; 
  signal UUT_N21 : STD_LOGIC; 
  signal UUT_N217_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_and0000 : STD_LOGIC; 
  signal UUT_N37_pack_1 : STD_LOGIC; 
  signal UUT_Dir_DXMUX_5608 : STD_LOGIC; 
  signal UUT_Dir_mux0000243 : STD_LOGIC; 
  signal UUT_Dir_mux000092_O_pack_1 : STD_LOGIC; 
  signal UUT_Dir_SRINV_5592 : STD_LOGIC; 
  signal UUT_Dir_CLKINV_5591 : STD_LOGIC; 
  signal N117 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0000_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_30_5658 : STD_LOGIC; 
  signal UUT_N0_pack_1 : STD_LOGIC; 
  signal UUT_writeCount_8_DXMUX_5687 : STD_LOGIC; 
  signal UUT_N31_pack_1 : STD_LOGIC; 
  signal UUT_writeCount_8_CLKINV_5671 : STD_LOGIC; 
  signal UUT_writeCount_9_DXMUX_5717 : STD_LOGIC; 
  signal UUT_N11_pack_1 : STD_LOGIC; 
  signal UUT_writeCount_9_CLKINV_5702 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_14_5742 : STD_LOGIC; 
  signal UUT_N46_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0002 : STD_LOGIC; 
  signal UUT_Dir_mux00012_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_0_DXMUX_5797 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_97 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_0_68_O_pack_1 : STD_LOGIC; 
  signal UUT_ack_count_0_SRINV_5781 : STD_LOGIC; 
  signal UUT_ack_count_0_CLKINV_5780 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_210_5823 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0015_pack_1 : STD_LOGIC; 
  signal UUT_N16 : STD_LOGIC; 
  signal UUT_ack_count_mux0000_10_20_O_pack_1 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_20_5871 : STD_LOGIC; 
  signal UUT_N40_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_or000017_5895 : STD_LOGIC; 
  signal UUT_shiftReg_or000012_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd4_DXMUX_6475 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In85 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In28_O_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd4_SRINV_6460 : STD_LOGIC; 
  signal UUT_nstate_FFd4_CLKINV_6459 : STD_LOGIC; 
  signal UUT_in_i2c_mux000034_6501 : STD_LOGIC; 
  signal UUT_in_i2c_mux000032_O_pack_1 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_125_6525 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_125_SW0_O_pack_1 : STD_LOGIC; 
  signal UUT_N41 : STD_LOGIC; 
  signal UUT_N101_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux000063_6573 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000211_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000144_6597 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000131_O_pack_1 : STD_LOGIC; 
  signal UUT_N3 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_145_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux000093_6645 : STD_LOGIC; 
  signal UUT_Dir_mux000035_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000190_6669 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000122_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000275_6693 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000266_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux000099_6717 : STD_LOGIC; 
  signal UUT_N22_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000287_6741 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000250_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_DXMUX_6772 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000314 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000216_O_pack_1 : STD_LOGIC; 
  signal UUT_in_i2c_SRINV_6757 : STD_LOGIC; 
  signal UUT_in_i2c_CLKINV_6756 : STD_LOGIC; 
  signal UUT_delay_count_11_DXMUX_6807 : STD_LOGIC; 
  signal UUT_delay_count_11_DYMUX_6796 : STD_LOGIC; 
  signal UUT_delay_count_11_CLKINV_6788 : STD_LOGIC; 
  signal UUT_delay_count_13_DXMUX_6841 : STD_LOGIC; 
  signal UUT_delay_count_13_DYMUX_6830 : STD_LOGIC; 
  signal UUT_delay_count_13_CLKINV_6822 : STD_LOGIC; 
  signal UUT_delay_count_15_DXMUX_6875 : STD_LOGIC; 
  signal UUT_delay_count_15_DYMUX_6864 : STD_LOGIC; 
  signal UUT_delay_count_15_CLKINV_6856 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000247_6909 : STD_LOGIC; 
  signal UUT_shiftReg_0_DYMUX_6899 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_23 : STD_LOGIC; 
  signal UUT_shiftReg_0_SRINV_6891 : STD_LOGIC; 
  signal UUT_shiftReg_0_CLKINV_6890 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_2_6942 : STD_LOGIC; 
  signal UUT_shiftReg_1_DYMUX_6933 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_1_22 : STD_LOGIC; 
  signal UUT_shiftReg_1_SRINV_6925 : STD_LOGIC; 
  signal UUT_shiftReg_1_CLKINV_6924 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_5_3_6975 : STD_LOGIC; 
  signal UUT_shiftReg_3_DYMUX_6966 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_32 : STD_LOGIC; 
  signal UUT_shiftReg_3_SRINV_6958 : STD_LOGIC; 
  signal UUT_shiftReg_3_CLKINV_6957 : STD_LOGIC; 
  signal N67 : STD_LOGIC; 
  signal UUT_shiftReg_4_DYMUX_6998 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_4_22 : STD_LOGIC; 
  signal UUT_shiftReg_4_SRINV_6990 : STD_LOGIC; 
  signal UUT_shiftReg_4_CLKINV_6989 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal UUT_shiftReg_6_DYMUX_7032 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_27 : STD_LOGIC; 
  signal UUT_shiftReg_6_SRINV_7024 : STD_LOGIC; 
  signal UUT_shiftReg_6_CLKINV_7023 : STD_LOGIC; 
  signal UUT_writeCount_1_DXMUX_7074 : STD_LOGIC; 
  signal UUT_writeCount_1_DYMUX_7063 : STD_LOGIC; 
  signal UUT_writeCount_1_CLKINV_7055 : STD_LOGIC; 
  signal UUT_writeCount_3_DXMUX_7108 : STD_LOGIC; 
  signal UUT_writeCount_3_DYMUX_7097 : STD_LOGIC; 
  signal UUT_writeCount_3_CLKINV_7089 : STD_LOGIC; 
  signal UUT_writeCount_5_DXMUX_7142 : STD_LOGIC; 
  signal UUT_writeCount_5_DYMUX_7131 : STD_LOGIC; 
  signal UUT_writeCount_5_CLKINV_7123 : STD_LOGIC; 
  signal UUT_writeCount_7_DXMUX_7176 : STD_LOGIC; 
  signal UUT_writeCount_7_DYMUX_7165 : STD_LOGIC; 
  signal UUT_writeCount_7_CLKINV_7157 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_not0001 : STD_LOGIC; 
  signal UUT_prevClk_DYMUX_7198 : STD_LOGIC; 
  signal UUT_prevClk_mux0000 : STD_LOGIC; 
  signal UUT_prevClk_CLKINV_7189 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_DYMUX_7226 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_and00001 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_SRINV_7216 : STD_LOGIC; 
  signal UUT_ClkRisingEdge_CLKINV_7215 : STD_LOGIC; 
  signal N77 : STD_LOGIC; 
  signal UUT_pstate_2_DYMUX_7249 : STD_LOGIC; 
  signal UUT_pstate_2_CLKINV_7241 : STD_LOGIC; 
  signal UUT_delay_count_0_DYMUX_7277 : STD_LOGIC; 
  signal UUT_delay_count_mux0000_0_1_7274 : STD_LOGIC; 
  signal UUT_delay_count_0_SRINV_7267 : STD_LOGIC; 
  signal UUT_delay_count_0_CLKINV_7266 : STD_LOGIC; 
  signal UUT_shiftReg_or000032_7309 : STD_LOGIC; 
  signal UUT_delay_count_1_DYMUX_7300 : STD_LOGIC; 
  signal UUT_delay_count_1_CLKINV_7292 : STD_LOGIC; 
  signal UUT_delay_count_3_DXMUX_7342 : STD_LOGIC; 
  signal UUT_delay_count_3_DYMUX_7331 : STD_LOGIC; 
  signal UUT_delay_count_3_CLKINV_7323 : STD_LOGIC; 
  signal UUT_delay_count_5_DXMUX_7376 : STD_LOGIC; 
  signal UUT_delay_count_5_DYMUX_7365 : STD_LOGIC; 
  signal UUT_delay_count_5_CLKINV_7357 : STD_LOGIC; 
  signal UUT_delay_count_7_DXMUX_7410 : STD_LOGIC; 
  signal UUT_delay_count_7_DYMUX_7399 : STD_LOGIC; 
  signal UUT_delay_count_7_CLKINV_7391 : STD_LOGIC; 
  signal UUT_delay_count_9_DXMUX_7444 : STD_LOGIC; 
  signal UUT_delay_count_9_DYMUX_7433 : STD_LOGIC; 
  signal UUT_delay_count_9_CLKINV_7425 : STD_LOGIC; 
  signal UUT_ack_count_11_DXMUX_7478 : STD_LOGIC; 
  signal UUT_ack_count_11_DYMUX_7467 : STD_LOGIC; 
  signal UUT_ack_count_11_CLKINV_7459 : STD_LOGIC; 
  signal UUT_ack_count_7_DXMUX_7512 : STD_LOGIC; 
  signal UUT_ack_count_7_DYMUX_7501 : STD_LOGIC; 
  signal UUT_ack_count_7_CLKINV_7493 : STD_LOGIC; 
  signal UUT_ack_count_3_DXMUX_7546 : STD_LOGIC; 
  signal UUT_ack_count_3_DYMUX_7535 : STD_LOGIC; 
  signal UUT_ack_count_3_CLKINV_7527 : STD_LOGIC; 
  signal UUT_ack_count_5_DXMUX_7580 : STD_LOGIC; 
  signal UUT_ack_count_5_DYMUX_7569 : STD_LOGIC; 
  signal UUT_ack_count_5_CLKINV_7561 : STD_LOGIC; 
  signal UUT_ack_count_9_DXMUX_7614 : STD_LOGIC; 
  signal UUT_ack_count_9_DYMUX_7603 : STD_LOGIC; 
  signal UUT_ack_count_9_CLKINV_7595 : STD_LOGIC; 
  signal UUT_writeCount_11_DXMUX_7648 : STD_LOGIC; 
  signal UUT_writeCount_11_DYMUX_7637 : STD_LOGIC; 
  signal UUT_writeCount_11_CLKINV_7629 : STD_LOGIC; 
  signal UUT_writeCount_13_DXMUX_7682 : STD_LOGIC; 
  signal UUT_writeCount_13_DYMUX_7671 : STD_LOGIC; 
  signal UUT_writeCount_13_CLKINV_7663 : STD_LOGIC; 
  signal UUT_writeCount_21_DXMUX_7716 : STD_LOGIC; 
  signal UUT_writeCount_21_DYMUX_7705 : STD_LOGIC; 
  signal UUT_writeCount_21_CLKINV_7697 : STD_LOGIC; 
  signal UUT_writeCount_15_DXMUX_7750 : STD_LOGIC; 
  signal UUT_writeCount_15_DYMUX_7739 : STD_LOGIC; 
  signal UUT_writeCount_15_CLKINV_7731 : STD_LOGIC; 
  signal UUT_writeCount_23_DXMUX_7784 : STD_LOGIC; 
  signal UUT_writeCount_23_DYMUX_7773 : STD_LOGIC; 
  signal UUT_writeCount_23_CLKINV_7765 : STD_LOGIC; 
  signal UUT_writeCount_30_DYMUX_7802 : STD_LOGIC; 
  signal UUT_writeCount_30_CLKINV_7794 : STD_LOGIC; 
  signal UUT_writeCount_17_DXMUX_7836 : STD_LOGIC; 
  signal UUT_writeCount_17_DYMUX_7825 : STD_LOGIC; 
  signal UUT_writeCount_17_CLKINV_7817 : STD_LOGIC; 
  signal UUT_writeCount_25_DXMUX_7870 : STD_LOGIC; 
  signal UUT_writeCount_25_DYMUX_7859 : STD_LOGIC; 
  signal UUT_writeCount_25_CLKINV_7851 : STD_LOGIC; 
  signal UUT_writeCount_19_DXMUX_7904 : STD_LOGIC; 
  signal UUT_writeCount_19_DYMUX_7893 : STD_LOGIC; 
  signal UUT_writeCount_19_CLKINV_7885 : STD_LOGIC; 
  signal UUT_writeCount_27_DXMUX_7938 : STD_LOGIC; 
  signal UUT_writeCount_27_DYMUX_7927 : STD_LOGIC; 
  signal UUT_writeCount_27_CLKINV_7919 : STD_LOGIC; 
  signal UUT_writeCount_29_DXMUX_7972 : STD_LOGIC; 
  signal UUT_writeCount_29_DYMUX_7961 : STD_LOGIC; 
  signal UUT_writeCount_29_CLKINV_7953 : STD_LOGIC; 
  signal sSW_3_or0000 : STD_LOGIC; 
  signal sSW_2_and0000 : STD_LOGIC; 
  signal sSW_2_and0001 : STD_LOGIC; 
  signal sSW_1_DXMUX_8024 : STD_LOGIC; 
  signal sSW_1_DYMUX_8019 : STD_LOGIC; 
  signal sSW_1_CLKINV_8017 : STD_LOGIC; 
  signal N51 : STD_LOGIC; 
  signal UUT_Dir_mux000062_8042 : STD_LOGIC; 
  signal sSW_2_DYMUX_8061 : STD_LOGIC; 
  signal sSW_2_SRINV_8059 : STD_LOGIC; 
  signal sSW_2_CLKINV_8058 : STD_LOGIC; 
  signal sSW_2_CEINV_8057 : STD_LOGIC; 
  signal sSW_3_DYMUX_8074 : STD_LOGIC; 
  signal sSW_3_SRINV_8072 : STD_LOGIC; 
  signal sSW_3_CLKINV_8071 : STD_LOGIC; 
  signal N73 : STD_LOGIC; 
  signal UUT_Dir_mux000057_8093 : STD_LOGIC; 
  signal N21 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0005 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux00009_8140 : STD_LOGIC; 
  signal N101 : STD_LOGIC; 
  signal UUT_N104 : STD_LOGIC; 
  signal UUT_N66 : STD_LOGIC; 
  signal UUT_N2119_8188 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux0000210_8220 : STD_LOGIC; 
  signal UUT_N2170_8212 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq00007_8232 : STD_LOGIC; 
  signal UUT_N112 : STD_LOGIC; 
  signal UUT_Dir_mux0000203_8247 : STD_LOGIC; 
  signal UUT_delay_count_and0000 : STD_LOGIC; 
  signal UUT_Dir_mux0000128_8273 : STD_LOGIC; 
  signal N91 : STD_LOGIC; 
  signal UUT_Dir_mux0000227_8297 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_7_8328 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0012 : STD_LOGIC; 
  signal N31 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In1_8364 : STD_LOGIC; 
  signal UUT_pstate_mux0000_7_1175_8355 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0011 : STD_LOGIC; 
  signal UUT_out_i2cclk_mux000050_8381 : STD_LOGIC; 
  signal CLK_sI2C_Clk_DYMUX_8398 : STD_LOGIC; 
  signal CLK_sI2C_Clk_CLKINV_8396 : STD_LOGIC; 
  signal CLK_sI2C_Clk_CEINV_8395 : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal N126 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq0000 : STD_LOGIC; 
  signal CLK_sI2C_Clk_cmp_eq000016_pack_1 : STD_LOGIC; 
  signal UUT_ClkEdge_1_DXMUX_8463 : STD_LOGIC; 
  signal UUT_ClkEdge_1_DYMUX_8458 : STD_LOGIC; 
  signal UUT_ClkEdge_1_CLKINV_8456 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_3_8 : STD_LOGIC; 
  signal UUT_nstate_FFd1_In0_8480 : STD_LOGIC; 
  signal N120 : STD_LOGIC; 
  signal N89 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_9_8536 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_0_2_pack_1 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_7_5_8560 : STD_LOGIC; 
  signal UUT_shiftReg_mux0000_6_11_8553 : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal UUT_nstate_cmp_eq0006 : STD_LOGIC; 
  signal N113 : STD_LOGIC; 
  signal UUT_in_i2c_mux0000158_8632 : STD_LOGIC; 
  signal N95 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_DYMUX_8642 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_SRINV_8640 : STD_LOGIC; 
  signal UUT_ClkFallingEdge_CLKINV_8639 : STD_LOGIC; 
  signal UUT_shiftReg_cmp_eq0000 : STD_LOGIC; 
  signal N33 : STD_LOGIC; 
  signal N39 : STD_LOGIC; 
  signal N37 : STD_LOGIC; 
  signal N40 : STD_LOGIC; 
  signal UUT_counter_0_DXMUX_8735 : STD_LOGIC; 
  signal UUT_counter_mux0000_4_47 : STD_LOGIC; 
  signal UUT_N62_pack_1 : STD_LOGIC; 
  signal UUT_counter_0_SRINV_8719 : STD_LOGIC; 
  signal UUT_counter_0_CLKINV_8718 : STD_LOGIC; 
  signal UUT_N106 : STD_LOGIC; 
  signal N36 : STD_LOGIC; 
  signal UUT_nstate_FFd3_In14_8785 : STD_LOGIC; 
  signal N128_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd2_In27_8821 : STD_LOGIC; 
  signal UUT_nstate_FFd2_In11_pack_1 : STD_LOGIC; 
  signal UUT_nstate_FFd4_In59_8833 : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal UUT_writeCount : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_writeCount_share0000 : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_Madd_writeCount_share0000_cy : STD_LOGIC_VECTOR ( 28 downto 0 ); 
  signal UUT_delay_count : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal UUT_ack_count : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal UUT_ack_count_share0000 : STD_LOGIC_VECTOR ( 11 downto 0 ); 
  signal UUT_delay_count_share0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal CLK_clk_div : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_shiftReg : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_counter : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal sSW : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal UUT_pstate : STD_LOGIC_VECTOR ( 4 downto 2 ); 
  signal UUT_ClkEdge : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal UUT_Madd_writeCount_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_shiftReg_cmp_eq0001_wg_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_shiftReg_cmp_eq0001_wg_cy : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_delay_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Madd_ack_count_share0000_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0002_lut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal UUT_Mcompar_nstate_cmp_gt0000_lut : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal CLK_Mcount_clk_div_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal UUT_pstate_mux0000 : STD_LOGIC_VECTOR ( 7 downto 5 ); 
  signal UUT_ack_count_mux0000 : STD_LOGIC_VECTOR ( 11 downto 1 ); 
  signal UUT_writeCount_mux0000 : STD_LOGIC_VECTOR ( 30 downto 0 ); 
  signal UUT_delay_count_mux0000 : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal UUT_Madd_counter_addsub0000_cy : STD_LOGIC_VECTOR ( 2 downto 2 ); 
begin
  UUT_writeCount_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y0"
    )
    port map (
      O => UUT_writeCount_share0000_0_LOGIC_ZERO_2687
    );
  UUT_writeCount_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X17Y0"
    )
    port map (
      O => UUT_writeCount_share0000_0_LOGIC_ONE_2704
    );
  UUT_writeCount_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_XORF_2705,
      O => UUT_writeCount_share0000(0)
    );
  UUT_writeCount_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y0"
    )
    port map (
      I0 => UUT_writeCount_share0000_0_CYINIT_2703,
      I1 => UUT_Madd_writeCount_share0000_lut(0),
      O => UUT_writeCount_share0000_0_XORF_2705
    );
  UUT_writeCount_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y0"
    )
    port map (
      IA => UUT_writeCount_share0000_0_LOGIC_ONE_2704,
      IB => UUT_writeCount_share0000_0_CYINIT_2703,
      SEL => UUT_writeCount_share0000_0_CYSELF_2694,
      O => UUT_Madd_writeCount_share0000_cy(0)
    );
  UUT_writeCount_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => UUT_writeCount_share0000_0_CYINIT_2703
    );
  UUT_writeCount_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_lut(0),
      O => UUT_writeCount_share0000_0_CYSELF_2694
    );
  UUT_writeCount_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_XORG_2690,
      O => UUT_writeCount_share0000(1)
    );
  UUT_writeCount_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y0"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(0),
      I1 => UUT_writeCount_share0000_0_G,
      O => UUT_writeCount_share0000_0_XORG_2690
    );
  UUT_writeCount_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_CYMUXG_2689,
      O => UUT_Madd_writeCount_share0000_cy(1)
    );
  UUT_writeCount_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X17Y0"
    )
    port map (
      IA => UUT_writeCount_share0000_0_LOGIC_ZERO_2687,
      IB => UUT_Madd_writeCount_share0000_cy(0),
      SEL => UUT_writeCount_share0000_0_CYSELG_2678,
      O => UUT_writeCount_share0000_0_CYMUXG_2689
    );
  UUT_writeCount_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_0_G,
      O => UUT_writeCount_share0000_0_CYSELG_2678
    );
  UUT_writeCount_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      O => UUT_writeCount_share0000_2_LOGIC_ZERO_2723
    );
  UUT_writeCount_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_XORF_2743,
      O => UUT_writeCount_share0000(2)
    );
  UUT_writeCount_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      I0 => UUT_writeCount_share0000_2_CYINIT_2742,
      I1 => UUT_writeCount_share0000_2_F,
      O => UUT_writeCount_share0000_2_XORF_2743
    );
  UUT_writeCount_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_LOGIC_ZERO_2723,
      IB => UUT_writeCount_share0000_2_CYINIT_2742,
      SEL => UUT_writeCount_share0000_2_CYSELF_2729,
      O => UUT_Madd_writeCount_share0000_cy(2)
    );
  UUT_writeCount_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_LOGIC_ZERO_2723,
      IB => UUT_writeCount_share0000_2_LOGIC_ZERO_2723,
      SEL => UUT_writeCount_share0000_2_CYSELF_2729,
      O => UUT_writeCount_share0000_2_CYMUXF2_2724
    );
  UUT_writeCount_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(1),
      O => UUT_writeCount_share0000_2_CYINIT_2742
    );
  UUT_writeCount_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_F,
      O => UUT_writeCount_share0000_2_CYSELF_2729
    );
  UUT_writeCount_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_XORG_2731,
      O => UUT_writeCount_share0000(3)
    );
  UUT_writeCount_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(2),
      I1 => UUT_writeCount_share0000_2_G,
      O => UUT_writeCount_share0000_2_XORG_2731
    );
  UUT_writeCount_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_CYMUXFAST_2728,
      O => UUT_Madd_writeCount_share0000_cy(3)
    );
  UUT_writeCount_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(1),
      O => UUT_writeCount_share0000_2_FASTCARRY_2726
    );
  UUT_writeCount_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      I0 => UUT_writeCount_share0000_2_CYSELG_2714,
      I1 => UUT_writeCount_share0000_2_CYSELF_2729,
      O => UUT_writeCount_share0000_2_CYAND_2727
    );
  UUT_writeCount_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_CYMUXG2_2725,
      IB => UUT_writeCount_share0000_2_FASTCARRY_2726,
      SEL => UUT_writeCount_share0000_2_CYAND_2727,
      O => UUT_writeCount_share0000_2_CYMUXFAST_2728
    );
  UUT_writeCount_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y1"
    )
    port map (
      IA => UUT_writeCount_share0000_2_LOGIC_ZERO_2723,
      IB => UUT_writeCount_share0000_2_CYMUXF2_2724,
      SEL => UUT_writeCount_share0000_2_CYSELG_2714,
      O => UUT_writeCount_share0000_2_CYMUXG2_2725
    );
  UUT_writeCount_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_2_G,
      O => UUT_writeCount_share0000_2_CYSELG_2714
    );
  UUT_writeCount_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      O => UUT_writeCount_share0000_4_LOGIC_ZERO_2761
    );
  UUT_writeCount_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_XORF_2781,
      O => UUT_writeCount_share0000(4)
    );
  UUT_writeCount_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      I0 => UUT_writeCount_share0000_4_CYINIT_2780,
      I1 => UUT_writeCount_share0000_4_F,
      O => UUT_writeCount_share0000_4_XORF_2781
    );
  UUT_writeCount_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_LOGIC_ZERO_2761,
      IB => UUT_writeCount_share0000_4_CYINIT_2780,
      SEL => UUT_writeCount_share0000_4_CYSELF_2767,
      O => UUT_Madd_writeCount_share0000_cy(4)
    );
  UUT_writeCount_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_LOGIC_ZERO_2761,
      IB => UUT_writeCount_share0000_4_LOGIC_ZERO_2761,
      SEL => UUT_writeCount_share0000_4_CYSELF_2767,
      O => UUT_writeCount_share0000_4_CYMUXF2_2762
    );
  UUT_writeCount_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(3),
      O => UUT_writeCount_share0000_4_CYINIT_2780
    );
  UUT_writeCount_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_F,
      O => UUT_writeCount_share0000_4_CYSELF_2767
    );
  UUT_writeCount_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_XORG_2769,
      O => UUT_writeCount_share0000(5)
    );
  UUT_writeCount_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(4),
      I1 => UUT_writeCount_share0000_4_G,
      O => UUT_writeCount_share0000_4_XORG_2769
    );
  UUT_writeCount_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_CYMUXFAST_2766,
      O => UUT_Madd_writeCount_share0000_cy(5)
    );
  UUT_writeCount_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(3),
      O => UUT_writeCount_share0000_4_FASTCARRY_2764
    );
  UUT_writeCount_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      I0 => UUT_writeCount_share0000_4_CYSELG_2752,
      I1 => UUT_writeCount_share0000_4_CYSELF_2767,
      O => UUT_writeCount_share0000_4_CYAND_2765
    );
  UUT_writeCount_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_CYMUXG2_2763,
      IB => UUT_writeCount_share0000_4_FASTCARRY_2764,
      SEL => UUT_writeCount_share0000_4_CYAND_2765,
      O => UUT_writeCount_share0000_4_CYMUXFAST_2766
    );
  UUT_writeCount_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y2"
    )
    port map (
      IA => UUT_writeCount_share0000_4_LOGIC_ZERO_2761,
      IB => UUT_writeCount_share0000_4_CYMUXF2_2762,
      SEL => UUT_writeCount_share0000_4_CYSELG_2752,
      O => UUT_writeCount_share0000_4_CYMUXG2_2763
    );
  UUT_writeCount_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_4_G,
      O => UUT_writeCount_share0000_4_CYSELG_2752
    );
  UUT_writeCount_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      O => UUT_writeCount_share0000_6_LOGIC_ZERO_2799
    );
  UUT_writeCount_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_XORF_2819,
      O => UUT_writeCount_share0000(6)
    );
  UUT_writeCount_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      I0 => UUT_writeCount_share0000_6_CYINIT_2818,
      I1 => UUT_writeCount_share0000_6_F,
      O => UUT_writeCount_share0000_6_XORF_2819
    );
  UUT_writeCount_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_LOGIC_ZERO_2799,
      IB => UUT_writeCount_share0000_6_CYINIT_2818,
      SEL => UUT_writeCount_share0000_6_CYSELF_2805,
      O => UUT_Madd_writeCount_share0000_cy(6)
    );
  UUT_writeCount_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_LOGIC_ZERO_2799,
      IB => UUT_writeCount_share0000_6_LOGIC_ZERO_2799,
      SEL => UUT_writeCount_share0000_6_CYSELF_2805,
      O => UUT_writeCount_share0000_6_CYMUXF2_2800
    );
  UUT_writeCount_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(5),
      O => UUT_writeCount_share0000_6_CYINIT_2818
    );
  UUT_writeCount_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_F,
      O => UUT_writeCount_share0000_6_CYSELF_2805
    );
  UUT_writeCount_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_XORG_2807,
      O => UUT_writeCount_share0000(7)
    );
  UUT_writeCount_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(6),
      I1 => UUT_writeCount_share0000_6_G,
      O => UUT_writeCount_share0000_6_XORG_2807
    );
  UUT_writeCount_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_CYMUXFAST_2804,
      O => UUT_Madd_writeCount_share0000_cy(7)
    );
  UUT_writeCount_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(5),
      O => UUT_writeCount_share0000_6_FASTCARRY_2802
    );
  UUT_writeCount_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      I0 => UUT_writeCount_share0000_6_CYSELG_2790,
      I1 => UUT_writeCount_share0000_6_CYSELF_2805,
      O => UUT_writeCount_share0000_6_CYAND_2803
    );
  UUT_writeCount_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_CYMUXG2_2801,
      IB => UUT_writeCount_share0000_6_FASTCARRY_2802,
      SEL => UUT_writeCount_share0000_6_CYAND_2803,
      O => UUT_writeCount_share0000_6_CYMUXFAST_2804
    );
  UUT_writeCount_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y3"
    )
    port map (
      IA => UUT_writeCount_share0000_6_LOGIC_ZERO_2799,
      IB => UUT_writeCount_share0000_6_CYMUXF2_2800,
      SEL => UUT_writeCount_share0000_6_CYSELG_2790,
      O => UUT_writeCount_share0000_6_CYMUXG2_2801
    );
  UUT_writeCount_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_6_G,
      O => UUT_writeCount_share0000_6_CYSELG_2790
    );
  UUT_writeCount_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      O => UUT_writeCount_share0000_8_LOGIC_ZERO_2837
    );
  UUT_writeCount_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_XORF_2857,
      O => UUT_writeCount_share0000(8)
    );
  UUT_writeCount_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      I0 => UUT_writeCount_share0000_8_CYINIT_2856,
      I1 => UUT_writeCount_share0000_8_F,
      O => UUT_writeCount_share0000_8_XORF_2857
    );
  UUT_writeCount_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_LOGIC_ZERO_2837,
      IB => UUT_writeCount_share0000_8_CYINIT_2856,
      SEL => UUT_writeCount_share0000_8_CYSELF_2843,
      O => UUT_Madd_writeCount_share0000_cy(8)
    );
  UUT_writeCount_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_LOGIC_ZERO_2837,
      IB => UUT_writeCount_share0000_8_LOGIC_ZERO_2837,
      SEL => UUT_writeCount_share0000_8_CYSELF_2843,
      O => UUT_writeCount_share0000_8_CYMUXF2_2838
    );
  UUT_writeCount_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(7),
      O => UUT_writeCount_share0000_8_CYINIT_2856
    );
  UUT_writeCount_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_F,
      O => UUT_writeCount_share0000_8_CYSELF_2843
    );
  UUT_writeCount_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_XORG_2845,
      O => UUT_writeCount_share0000(9)
    );
  UUT_writeCount_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(8),
      I1 => UUT_writeCount_share0000_8_G,
      O => UUT_writeCount_share0000_8_XORG_2845
    );
  UUT_writeCount_share0000_8_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_CYMUXFAST_2842,
      O => UUT_Madd_writeCount_share0000_cy(9)
    );
  UUT_writeCount_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(7),
      O => UUT_writeCount_share0000_8_FASTCARRY_2840
    );
  UUT_writeCount_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      I0 => UUT_writeCount_share0000_8_CYSELG_2828,
      I1 => UUT_writeCount_share0000_8_CYSELF_2843,
      O => UUT_writeCount_share0000_8_CYAND_2841
    );
  UUT_writeCount_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_CYMUXG2_2839,
      IB => UUT_writeCount_share0000_8_FASTCARRY_2840,
      SEL => UUT_writeCount_share0000_8_CYAND_2841,
      O => UUT_writeCount_share0000_8_CYMUXFAST_2842
    );
  UUT_writeCount_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y4"
    )
    port map (
      IA => UUT_writeCount_share0000_8_LOGIC_ZERO_2837,
      IB => UUT_writeCount_share0000_8_CYMUXF2_2838,
      SEL => UUT_writeCount_share0000_8_CYSELG_2828,
      O => UUT_writeCount_share0000_8_CYMUXG2_2839
    );
  UUT_writeCount_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_8_G,
      O => UUT_writeCount_share0000_8_CYSELG_2828
    );
  UUT_writeCount_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      O => UUT_writeCount_share0000_10_LOGIC_ZERO_2875
    );
  UUT_writeCount_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_XORF_2895,
      O => UUT_writeCount_share0000(10)
    );
  UUT_writeCount_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      I0 => UUT_writeCount_share0000_10_CYINIT_2894,
      I1 => UUT_writeCount_share0000_10_F,
      O => UUT_writeCount_share0000_10_XORF_2895
    );
  UUT_writeCount_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_LOGIC_ZERO_2875,
      IB => UUT_writeCount_share0000_10_CYINIT_2894,
      SEL => UUT_writeCount_share0000_10_CYSELF_2881,
      O => UUT_Madd_writeCount_share0000_cy(10)
    );
  UUT_writeCount_share0000_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_LOGIC_ZERO_2875,
      IB => UUT_writeCount_share0000_10_LOGIC_ZERO_2875,
      SEL => UUT_writeCount_share0000_10_CYSELF_2881,
      O => UUT_writeCount_share0000_10_CYMUXF2_2876
    );
  UUT_writeCount_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(9),
      O => UUT_writeCount_share0000_10_CYINIT_2894
    );
  UUT_writeCount_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_F,
      O => UUT_writeCount_share0000_10_CYSELF_2881
    );
  UUT_writeCount_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_XORG_2883,
      O => UUT_writeCount_share0000(11)
    );
  UUT_writeCount_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(10),
      I1 => UUT_writeCount_share0000_10_G,
      O => UUT_writeCount_share0000_10_XORG_2883
    );
  UUT_writeCount_share0000_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_CYMUXFAST_2880,
      O => UUT_Madd_writeCount_share0000_cy(11)
    );
  UUT_writeCount_share0000_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(9),
      O => UUT_writeCount_share0000_10_FASTCARRY_2878
    );
  UUT_writeCount_share0000_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      I0 => UUT_writeCount_share0000_10_CYSELG_2866,
      I1 => UUT_writeCount_share0000_10_CYSELF_2881,
      O => UUT_writeCount_share0000_10_CYAND_2879
    );
  UUT_writeCount_share0000_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_CYMUXG2_2877,
      IB => UUT_writeCount_share0000_10_FASTCARRY_2878,
      SEL => UUT_writeCount_share0000_10_CYAND_2879,
      O => UUT_writeCount_share0000_10_CYMUXFAST_2880
    );
  UUT_writeCount_share0000_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y5"
    )
    port map (
      IA => UUT_writeCount_share0000_10_LOGIC_ZERO_2875,
      IB => UUT_writeCount_share0000_10_CYMUXF2_2876,
      SEL => UUT_writeCount_share0000_10_CYSELG_2866,
      O => UUT_writeCount_share0000_10_CYMUXG2_2877
    );
  UUT_writeCount_share0000_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_10_G,
      O => UUT_writeCount_share0000_10_CYSELG_2866
    );
  UUT_ack_count_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      O => UUT_ack_count_share0000_8_LOGIC_ZERO_3527
    );
  UUT_ack_count_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_XORF_3547,
      O => UUT_ack_count_share0000(8)
    );
  UUT_ack_count_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      I0 => UUT_ack_count_share0000_8_CYINIT_3546,
      I1 => UUT_ack_count_share0000_8_F,
      O => UUT_ack_count_share0000_8_XORF_3547
    );
  UUT_ack_count_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_8_LOGIC_ZERO_3527,
      IB => UUT_ack_count_share0000_8_CYINIT_3546,
      SEL => UUT_ack_count_share0000_8_CYSELF_3533,
      O => UUT_Madd_ack_count_share0000_cy_8_Q
    );
  UUT_ack_count_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_8_LOGIC_ZERO_3527,
      IB => UUT_ack_count_share0000_8_LOGIC_ZERO_3527,
      SEL => UUT_ack_count_share0000_8_CYSELF_3533,
      O => UUT_ack_count_share0000_8_CYMUXF2_3528
    );
  UUT_ack_count_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_7_Q,
      O => UUT_ack_count_share0000_8_CYINIT_3546
    );
  UUT_ack_count_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_F,
      O => UUT_ack_count_share0000_8_CYSELF_3533
    );
  UUT_ack_count_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_XORG_3535,
      O => UUT_ack_count_share0000(9)
    );
  UUT_ack_count_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_8_Q,
      I1 => UUT_ack_count_share0000_8_G,
      O => UUT_ack_count_share0000_8_XORG_3535
    );
  UUT_ack_count_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_7_Q,
      O => UUT_ack_count_share0000_8_FASTCARRY_3530
    );
  UUT_ack_count_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      I0 => UUT_ack_count_share0000_8_CYSELG_3518,
      I1 => UUT_ack_count_share0000_8_CYSELF_3533,
      O => UUT_ack_count_share0000_8_CYAND_3531
    );
  UUT_ack_count_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_8_CYMUXG2_3529,
      IB => UUT_ack_count_share0000_8_FASTCARRY_3530,
      SEL => UUT_ack_count_share0000_8_CYAND_3531,
      O => UUT_ack_count_share0000_8_CYMUXFAST_3532
    );
  UUT_ack_count_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y60"
    )
    port map (
      IA => UUT_ack_count_share0000_8_LOGIC_ZERO_3527,
      IB => UUT_ack_count_share0000_8_CYMUXF2_3528,
      SEL => UUT_ack_count_share0000_8_CYSELG_3518,
      O => UUT_ack_count_share0000_8_CYMUXG2_3529
    );
  UUT_ack_count_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_G,
      O => UUT_ack_count_share0000_8_CYSELG_3518
    );
  UUT_ack_count_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y61"
    )
    port map (
      O => UUT_ack_count_share0000_10_LOGIC_ZERO_3577
    );
  UUT_ack_count_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_10_XORF_3578,
      O => UUT_ack_count_share0000(10)
    );
  UUT_ack_count_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y61"
    )
    port map (
      I0 => UUT_ack_count_share0000_10_CYINIT_3576,
      I1 => UUT_ack_count_share0000_10_F,
      O => UUT_ack_count_share0000_10_XORF_3578
    );
  UUT_ack_count_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y61"
    )
    port map (
      IA => UUT_ack_count_share0000_10_LOGIC_ZERO_3577,
      IB => UUT_ack_count_share0000_10_CYINIT_3576,
      SEL => UUT_ack_count_share0000_10_CYSELF_3567,
      O => UUT_Madd_ack_count_share0000_cy_10_Q
    );
  UUT_ack_count_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_8_CYMUXFAST_3532,
      O => UUT_ack_count_share0000_10_CYINIT_3576
    );
  UUT_ack_count_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_10_F,
      O => UUT_ack_count_share0000_10_CYSELF_3567
    );
  UUT_ack_count_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_10_XORG_3564,
      O => UUT_ack_count_share0000(11)
    );
  UUT_ack_count_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y61"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_10_Q,
      I1 => UUT_ack_count_11_rt_3561,
      O => UUT_ack_count_share0000_10_XORG_3564
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X15Y53"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3597
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X15Y53"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3609
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X15Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ZERO_3609,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT_3608,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF_3602,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_0_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X15Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYINIT_3608
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X15Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_3601,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELF_3602
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X15Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_LOGIC_ONE_3597,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_0_1,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG_3589,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG_3599
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X15Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_3588,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYSELG_3589
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X15Y54"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3627
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y54"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3627,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3627,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3633,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2_3628
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X15Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_3634,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3633
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST_3632,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X15Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_1_1_CYMUXG_3599,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY_3630
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X15Y54"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3619,
      I1 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELF_3633,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND_3631
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X15Y54"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2_3629,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_FASTCARRY_3630,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYAND_3631,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXFAST_3632
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y54"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_LOGIC_ZERO_3627,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXF2_3628,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3619,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYMUXG2_3629
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X15Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_3618,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1_CYSELG_3619
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X15Y5"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3656
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X15Y5"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3656,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT_3668,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF_3661,
      O => UUT_shiftReg_cmp_eq0001_wg_cy(0)
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X15Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYINIT_3668
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X15Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(0),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELF_3661
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X15Y5"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_1_LOGIC_ZERO_3656,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy(0),
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG_3650,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG_3658
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X15Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(1),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYSELG_3650
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X15Y6"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3686
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y6"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3686,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3686,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3692,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2_3687
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X15Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(2),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3692
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X15Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_cy_1_CYMUXG_3658,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY_3689
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X15Y6"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3680,
      I1 => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELF_3692,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND_3690
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X15Y6"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2_3688,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_3_FASTCARRY_3689,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYAND_3690,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST_3691
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y6"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_3_LOGIC_ZERO_3686,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXF2_3687,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3680,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXG2_3688
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X15Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(3),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYSELG_3680
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X15Y7"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3716
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y7"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3716,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3716,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3722,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2_3717
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X15Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(4),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3722
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X15Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_cy_3_CYMUXFAST_3691,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY_3719
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X15Y7"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3710,
      I1 => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELF_3722,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND_3720
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X15Y7"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2_3718,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_5_FASTCARRY_3719,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYAND_3720,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST_3721
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y7"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_wg_cy_5_LOGIC_ZERO_3716,
      IB => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXF2_3717,
      SEL => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3710,
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXG2_3718
    );
  UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X15Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(5),
      O => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYSELG_3710
    );
  UUT_shiftReg_cmp_eq0001_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X15Y8"
    )
    port map (
      O => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3746
    );
  UUT_shiftReg_cmp_eq0001_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y8"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3746,
      IB => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3746,
      SEL => UUT_shiftReg_cmp_eq0001_CYSELF_3752,
      O => UUT_shiftReg_cmp_eq0001_CYMUXF2_3747
    );
  UUT_shiftReg_cmp_eq0001_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X15Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(6),
      O => UUT_shiftReg_cmp_eq0001_CYSELF_3752
    );
  UUT_shiftReg_cmp_eq0001_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_CYMUXFAST_3751,
      O => UUT_shiftReg_cmp_eq0001
    );
  UUT_shiftReg_cmp_eq0001_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X15Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_cy_5_CYMUXFAST_3721,
      O => UUT_shiftReg_cmp_eq0001_FASTCARRY_3749
    );
  UUT_shiftReg_cmp_eq0001_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X15Y8"
    )
    port map (
      I0 => UUT_shiftReg_cmp_eq0001_CYSELG_3740,
      I1 => UUT_shiftReg_cmp_eq0001_CYSELF_3752,
      O => UUT_shiftReg_cmp_eq0001_CYAND_3750
    );
  UUT_shiftReg_cmp_eq0001_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X15Y8"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_CYMUXG2_3748,
      IB => UUT_shiftReg_cmp_eq0001_FASTCARRY_3749,
      SEL => UUT_shiftReg_cmp_eq0001_CYAND_3750,
      O => UUT_shiftReg_cmp_eq0001_CYMUXFAST_3751
    );
  UUT_shiftReg_cmp_eq0001_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X15Y8"
    )
    port map (
      IA => UUT_shiftReg_cmp_eq0001_LOGIC_ZERO_3746,
      IB => UUT_shiftReg_cmp_eq0001_CYMUXF2_3747,
      SEL => UUT_shiftReg_cmp_eq0001_CYSELG_3740,
      O => UUT_shiftReg_cmp_eq0001_CYMUXG2_3748
    );
  UUT_shiftReg_cmp_eq0001_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X15Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0001_wg_lut(7),
      O => UUT_shiftReg_cmp_eq0001_CYSELG_3740
    );
  UUT_delay_count_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y15"
    )
    port map (
      O => UUT_delay_count_share0000_0_LOGIC_ZERO_3775
    );
  UUT_delay_count_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X33Y15"
    )
    port map (
      O => UUT_delay_count_share0000_0_LOGIC_ONE_3792
    );
  UUT_delay_count_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_XORF_3793,
      O => UUT_delay_count_share0000(0)
    );
  UUT_delay_count_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y15"
    )
    port map (
      I0 => UUT_delay_count_share0000_0_CYINIT_3791,
      I1 => UUT_Madd_delay_count_share0000_lut(0),
      O => UUT_delay_count_share0000_0_XORF_3793
    );
  UUT_delay_count_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y15"
    )
    port map (
      IA => UUT_delay_count_share0000_0_LOGIC_ONE_3792,
      IB => UUT_delay_count_share0000_0_CYINIT_3791,
      SEL => UUT_delay_count_share0000_0_CYSELF_3782,
      O => UUT_Madd_delay_count_share0000_cy_0_Q
    );
  UUT_delay_count_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => UUT_delay_count_share0000_0_CYINIT_3791
    );
  UUT_delay_count_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_lut(0),
      O => UUT_delay_count_share0000_0_CYSELF_3782
    );
  UUT_delay_count_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_XORG_3778,
      O => UUT_delay_count_share0000(1)
    );
  UUT_delay_count_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y15"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_0_Q,
      I1 => UUT_delay_count_share0000_0_G,
      O => UUT_delay_count_share0000_0_XORG_3778
    );
  UUT_delay_count_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_CYMUXG_3777,
      O => UUT_Madd_delay_count_share0000_cy_1_Q
    );
  UUT_delay_count_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X33Y15"
    )
    port map (
      IA => UUT_delay_count_share0000_0_LOGIC_ZERO_3775,
      IB => UUT_Madd_delay_count_share0000_cy_0_Q,
      SEL => UUT_delay_count_share0000_0_CYSELG_3766,
      O => UUT_delay_count_share0000_0_CYMUXG_3777
    );
  UUT_delay_count_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_0_G,
      O => UUT_delay_count_share0000_0_CYSELG_3766
    );
  UUT_delay_count_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      O => UUT_delay_count_share0000_2_LOGIC_ZERO_3811
    );
  UUT_delay_count_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_XORF_3831,
      O => UUT_delay_count_share0000(2)
    );
  UUT_delay_count_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      I0 => UUT_delay_count_share0000_2_CYINIT_3830,
      I1 => UUT_delay_count_share0000_2_F,
      O => UUT_delay_count_share0000_2_XORF_3831
    );
  UUT_delay_count_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      IA => UUT_delay_count_share0000_2_LOGIC_ZERO_3811,
      IB => UUT_delay_count_share0000_2_CYINIT_3830,
      SEL => UUT_delay_count_share0000_2_CYSELF_3817,
      O => UUT_Madd_delay_count_share0000_cy_2_Q
    );
  UUT_delay_count_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      IA => UUT_delay_count_share0000_2_LOGIC_ZERO_3811,
      IB => UUT_delay_count_share0000_2_LOGIC_ZERO_3811,
      SEL => UUT_delay_count_share0000_2_CYSELF_3817,
      O => UUT_delay_count_share0000_2_CYMUXF2_3812
    );
  UUT_delay_count_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_1_Q,
      O => UUT_delay_count_share0000_2_CYINIT_3830
    );
  UUT_delay_count_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_F,
      O => UUT_delay_count_share0000_2_CYSELF_3817
    );
  UUT_delay_count_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_XORG_3819,
      O => UUT_delay_count_share0000(3)
    );
  UUT_delay_count_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_2_Q,
      I1 => UUT_delay_count_share0000_2_G,
      O => UUT_delay_count_share0000_2_XORG_3819
    );
  UUT_delay_count_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_CYMUXFAST_3816,
      O => UUT_Madd_delay_count_share0000_cy_3_Q
    );
  UUT_delay_count_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_1_Q,
      O => UUT_delay_count_share0000_2_FASTCARRY_3814
    );
  UUT_delay_count_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      I0 => UUT_delay_count_share0000_2_CYSELG_3802,
      I1 => UUT_delay_count_share0000_2_CYSELF_3817,
      O => UUT_delay_count_share0000_2_CYAND_3815
    );
  UUT_delay_count_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      IA => UUT_delay_count_share0000_2_CYMUXG2_3813,
      IB => UUT_delay_count_share0000_2_FASTCARRY_3814,
      SEL => UUT_delay_count_share0000_2_CYAND_3815,
      O => UUT_delay_count_share0000_2_CYMUXFAST_3816
    );
  UUT_delay_count_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y16"
    )
    port map (
      IA => UUT_delay_count_share0000_2_LOGIC_ZERO_3811,
      IB => UUT_delay_count_share0000_2_CYMUXF2_3812,
      SEL => UUT_delay_count_share0000_2_CYSELG_3802,
      O => UUT_delay_count_share0000_2_CYMUXG2_3813
    );
  UUT_delay_count_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_2_G,
      O => UUT_delay_count_share0000_2_CYSELG_3802
    );
  UUT_writeCount_share0000_28_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      O => UUT_writeCount_share0000_28_LOGIC_ZERO_3217
    );
  UUT_writeCount_share0000_28_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_XORF_3237,
      O => UUT_writeCount_share0000(28)
    );
  UUT_writeCount_share0000_28_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      I0 => UUT_writeCount_share0000_28_CYINIT_3236,
      I1 => UUT_writeCount_share0000_28_F,
      O => UUT_writeCount_share0000_28_XORF_3237
    );
  UUT_writeCount_share0000_28_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_LOGIC_ZERO_3217,
      IB => UUT_writeCount_share0000_28_CYINIT_3236,
      SEL => UUT_writeCount_share0000_28_CYSELF_3223,
      O => UUT_Madd_writeCount_share0000_cy(28)
    );
  UUT_writeCount_share0000_28_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_LOGIC_ZERO_3217,
      IB => UUT_writeCount_share0000_28_LOGIC_ZERO_3217,
      SEL => UUT_writeCount_share0000_28_CYSELF_3223,
      O => UUT_writeCount_share0000_28_CYMUXF2_3218
    );
  UUT_writeCount_share0000_28_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(27),
      O => UUT_writeCount_share0000_28_CYINIT_3236
    );
  UUT_writeCount_share0000_28_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_F,
      O => UUT_writeCount_share0000_28_CYSELF_3223
    );
  UUT_writeCount_share0000_28_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_XORG_3225,
      O => UUT_writeCount_share0000(29)
    );
  UUT_writeCount_share0000_28_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(28),
      I1 => UUT_writeCount_share0000_28_G,
      O => UUT_writeCount_share0000_28_XORG_3225
    );
  UUT_writeCount_share0000_28_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(27),
      O => UUT_writeCount_share0000_28_FASTCARRY_3220
    );
  UUT_writeCount_share0000_28_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      I0 => UUT_writeCount_share0000_28_CYSELG_3208,
      I1 => UUT_writeCount_share0000_28_CYSELF_3223,
      O => UUT_writeCount_share0000_28_CYAND_3221
    );
  UUT_writeCount_share0000_28_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_CYMUXG2_3219,
      IB => UUT_writeCount_share0000_28_FASTCARRY_3220,
      SEL => UUT_writeCount_share0000_28_CYAND_3221,
      O => UUT_writeCount_share0000_28_CYMUXFAST_3222
    );
  UUT_writeCount_share0000_28_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y14"
    )
    port map (
      IA => UUT_writeCount_share0000_28_LOGIC_ZERO_3217,
      IB => UUT_writeCount_share0000_28_CYMUXF2_3218,
      SEL => UUT_writeCount_share0000_28_CYSELG_3208,
      O => UUT_writeCount_share0000_28_CYMUXG2_3219
    );
  UUT_writeCount_share0000_28_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_G,
      O => UUT_writeCount_share0000_28_CYSELG_3208
    );
  UUT_writeCount_share0000_30_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_30_XORF_3252,
      O => UUT_writeCount_share0000(30)
    );
  UUT_writeCount_share0000_30_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y15"
    )
    port map (
      I0 => UUT_writeCount_share0000_30_CYINIT_3251,
      I1 => UUT_writeCount_30_rt_3249,
      O => UUT_writeCount_share0000_30_XORF_3252
    );
  UUT_writeCount_share0000_30_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_28_CYMUXFAST_3222,
      O => UUT_writeCount_share0000_30_CYINIT_3251
    );
  UUT_writeCount_30_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y15"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(30),
      O => UUT_writeCount_30_rt_3249
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y13"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE_3268
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y13"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO_3283
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X31Y13"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ZERO_3283,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT_3282,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF_3273,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X31Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYINIT_3282
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_2_rt_3272,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELF_3273
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X31Y13"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_LOGIC_ONE_3268,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_0_Q,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG_3260,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG_3270
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_3259,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYSELG_3260
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y14"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE_3299
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y14"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3314
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y14"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3314,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ZERO_3314,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3305,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2_3300
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_3306,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3305
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X31Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_cy_1_CYMUXG_3270,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY_3302
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X31Y14"
    )
    port map (
      I0 => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3290,
      I1 => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELF_3305,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND_3303
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X31Y14"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2_3301,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_FASTCARRY_3302,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYAND_3303,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST_3304
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y14"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_LOGIC_ONE_3299,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXF2_3300,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3290,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXG2_3301
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYSELG_3290
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y15"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE_3329
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y15"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3345
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y15"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3345,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ZERO_3345,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3335,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2_3330
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_8_rt_3336,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3335
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X31Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_cy_3_CYMUXFAST_3304,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY_3332
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X31Y15"
    )
    port map (
      I0 => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3323,
      I1 => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELF_3335,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND_3333
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X31Y15"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2_3331,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_FASTCARRY_3332,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYAND_3333,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST_3334
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y15"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_LOGIC_ONE_3329,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXF2_3330,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3323,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXG2_3331
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_3322,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYSELG_3323
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y16"
    )
    port map (
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE_3360
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X31Y16"
    )
    port map (
      IA => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_LOGIC_ONE_3360,
      IB => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT_3359,
      SEL => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF_3352,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X31Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_cy_5_CYMUXFAST_3334,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYINIT_3359
    );
  UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_3351,
      O => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_CYSELF_3352
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q : X_LUT4
    generic map(
      INIT => X"0011",
      LOC => "SLICE_X31Y16"
    )
    port map (
      ADR0 => UUT_delay_count(13),
      ADR1 => UUT_delay_count(14),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(15),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_6_Q_3351
    );
  UUT_ack_count_share0000_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y56"
    )
    port map (
      O => UUT_ack_count_share0000_0_LOGIC_ZERO_3377
    );
  UUT_ack_count_share0000_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X17Y56"
    )
    port map (
      O => UUT_ack_count_share0000_0_LOGIC_ONE_3394
    );
  UUT_ack_count_share0000_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_XORF_3395,
      O => UUT_ack_count_share0000(0)
    );
  UUT_ack_count_share0000_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y56"
    )
    port map (
      I0 => UUT_ack_count_share0000_0_CYINIT_3393,
      I1 => UUT_Madd_ack_count_share0000_lut(0),
      O => UUT_ack_count_share0000_0_XORF_3395
    );
  UUT_ack_count_share0000_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y56"
    )
    port map (
      IA => UUT_ack_count_share0000_0_LOGIC_ONE_3394,
      IB => UUT_ack_count_share0000_0_CYINIT_3393,
      SEL => UUT_ack_count_share0000_0_CYSELF_3384,
      O => UUT_Madd_ack_count_share0000_cy_0_Q
    );
  UUT_ack_count_share0000_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => UUT_ack_count_share0000_0_CYINIT_3393
    );
  UUT_ack_count_share0000_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_lut(0),
      O => UUT_ack_count_share0000_0_CYSELF_3384
    );
  UUT_ack_count_share0000_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_XORG_3380,
      O => UUT_ack_count_share0000(1)
    );
  UUT_ack_count_share0000_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y56"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_0_Q,
      I1 => UUT_ack_count_share0000_0_G,
      O => UUT_ack_count_share0000_0_XORG_3380
    );
  UUT_ack_count_share0000_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_CYMUXG_3379,
      O => UUT_Madd_ack_count_share0000_cy_1_Q
    );
  UUT_ack_count_share0000_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X17Y56"
    )
    port map (
      IA => UUT_ack_count_share0000_0_LOGIC_ZERO_3377,
      IB => UUT_Madd_ack_count_share0000_cy_0_Q,
      SEL => UUT_ack_count_share0000_0_CYSELG_3368,
      O => UUT_ack_count_share0000_0_CYMUXG_3379
    );
  UUT_ack_count_share0000_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_0_G,
      O => UUT_ack_count_share0000_0_CYSELG_3368
    );
  UUT_ack_count_share0000_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      O => UUT_ack_count_share0000_2_LOGIC_ZERO_3413
    );
  UUT_ack_count_share0000_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_XORF_3433,
      O => UUT_ack_count_share0000(2)
    );
  UUT_ack_count_share0000_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      I0 => UUT_ack_count_share0000_2_CYINIT_3432,
      I1 => UUT_ack_count_share0000_2_F,
      O => UUT_ack_count_share0000_2_XORF_3433
    );
  UUT_ack_count_share0000_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      IA => UUT_ack_count_share0000_2_LOGIC_ZERO_3413,
      IB => UUT_ack_count_share0000_2_CYINIT_3432,
      SEL => UUT_ack_count_share0000_2_CYSELF_3419,
      O => UUT_Madd_ack_count_share0000_cy_2_Q
    );
  UUT_ack_count_share0000_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      IA => UUT_ack_count_share0000_2_LOGIC_ZERO_3413,
      IB => UUT_ack_count_share0000_2_LOGIC_ZERO_3413,
      SEL => UUT_ack_count_share0000_2_CYSELF_3419,
      O => UUT_ack_count_share0000_2_CYMUXF2_3414
    );
  UUT_ack_count_share0000_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_1_Q,
      O => UUT_ack_count_share0000_2_CYINIT_3432
    );
  UUT_ack_count_share0000_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_F,
      O => UUT_ack_count_share0000_2_CYSELF_3419
    );
  UUT_ack_count_share0000_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_XORG_3421,
      O => UUT_ack_count_share0000(3)
    );
  UUT_ack_count_share0000_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_2_Q,
      I1 => UUT_ack_count_share0000_2_G,
      O => UUT_ack_count_share0000_2_XORG_3421
    );
  UUT_ack_count_share0000_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_CYMUXFAST_3418,
      O => UUT_Madd_ack_count_share0000_cy_3_Q
    );
  UUT_ack_count_share0000_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_1_Q,
      O => UUT_ack_count_share0000_2_FASTCARRY_3416
    );
  UUT_ack_count_share0000_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      I0 => UUT_ack_count_share0000_2_CYSELG_3404,
      I1 => UUT_ack_count_share0000_2_CYSELF_3419,
      O => UUT_ack_count_share0000_2_CYAND_3417
    );
  UUT_ack_count_share0000_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      IA => UUT_ack_count_share0000_2_CYMUXG2_3415,
      IB => UUT_ack_count_share0000_2_FASTCARRY_3416,
      SEL => UUT_ack_count_share0000_2_CYAND_3417,
      O => UUT_ack_count_share0000_2_CYMUXFAST_3418
    );
  UUT_ack_count_share0000_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y57"
    )
    port map (
      IA => UUT_ack_count_share0000_2_LOGIC_ZERO_3413,
      IB => UUT_ack_count_share0000_2_CYMUXF2_3414,
      SEL => UUT_ack_count_share0000_2_CYSELG_3404,
      O => UUT_ack_count_share0000_2_CYMUXG2_3415
    );
  UUT_ack_count_share0000_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_2_G,
      O => UUT_ack_count_share0000_2_CYSELG_3404
    );
  UUT_ack_count_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      O => UUT_ack_count_share0000_4_LOGIC_ZERO_3451
    );
  UUT_ack_count_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_XORF_3471,
      O => UUT_ack_count_share0000(4)
    );
  UUT_ack_count_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      I0 => UUT_ack_count_share0000_4_CYINIT_3470,
      I1 => UUT_ack_count_share0000_4_F,
      O => UUT_ack_count_share0000_4_XORF_3471
    );
  UUT_ack_count_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      IA => UUT_ack_count_share0000_4_LOGIC_ZERO_3451,
      IB => UUT_ack_count_share0000_4_CYINIT_3470,
      SEL => UUT_ack_count_share0000_4_CYSELF_3457,
      O => UUT_Madd_ack_count_share0000_cy_4_Q
    );
  UUT_ack_count_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      IA => UUT_ack_count_share0000_4_LOGIC_ZERO_3451,
      IB => UUT_ack_count_share0000_4_LOGIC_ZERO_3451,
      SEL => UUT_ack_count_share0000_4_CYSELF_3457,
      O => UUT_ack_count_share0000_4_CYMUXF2_3452
    );
  UUT_ack_count_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_3_Q,
      O => UUT_ack_count_share0000_4_CYINIT_3470
    );
  UUT_ack_count_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_F,
      O => UUT_ack_count_share0000_4_CYSELF_3457
    );
  UUT_ack_count_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_XORG_3459,
      O => UUT_ack_count_share0000(5)
    );
  UUT_ack_count_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_4_Q,
      I1 => UUT_ack_count_share0000_4_G,
      O => UUT_ack_count_share0000_4_XORG_3459
    );
  UUT_ack_count_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_CYMUXFAST_3456,
      O => UUT_Madd_ack_count_share0000_cy_5_Q
    );
  UUT_ack_count_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_3_Q,
      O => UUT_ack_count_share0000_4_FASTCARRY_3454
    );
  UUT_ack_count_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      I0 => UUT_ack_count_share0000_4_CYSELG_3442,
      I1 => UUT_ack_count_share0000_4_CYSELF_3457,
      O => UUT_ack_count_share0000_4_CYAND_3455
    );
  UUT_ack_count_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      IA => UUT_ack_count_share0000_4_CYMUXG2_3453,
      IB => UUT_ack_count_share0000_4_FASTCARRY_3454,
      SEL => UUT_ack_count_share0000_4_CYAND_3455,
      O => UUT_ack_count_share0000_4_CYMUXFAST_3456
    );
  UUT_ack_count_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y58"
    )
    port map (
      IA => UUT_ack_count_share0000_4_LOGIC_ZERO_3451,
      IB => UUT_ack_count_share0000_4_CYMUXF2_3452,
      SEL => UUT_ack_count_share0000_4_CYSELG_3442,
      O => UUT_ack_count_share0000_4_CYMUXG2_3453
    );
  UUT_ack_count_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_4_G,
      O => UUT_ack_count_share0000_4_CYSELG_3442
    );
  UUT_ack_count_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      O => UUT_ack_count_share0000_6_LOGIC_ZERO_3489
    );
  UUT_ack_count_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_XORF_3509,
      O => UUT_ack_count_share0000(6)
    );
  UUT_ack_count_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      I0 => UUT_ack_count_share0000_6_CYINIT_3508,
      I1 => UUT_ack_count_share0000_6_F,
      O => UUT_ack_count_share0000_6_XORF_3509
    );
  UUT_ack_count_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      IA => UUT_ack_count_share0000_6_LOGIC_ZERO_3489,
      IB => UUT_ack_count_share0000_6_CYINIT_3508,
      SEL => UUT_ack_count_share0000_6_CYSELF_3495,
      O => UUT_Madd_ack_count_share0000_cy_6_Q
    );
  UUT_ack_count_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      IA => UUT_ack_count_share0000_6_LOGIC_ZERO_3489,
      IB => UUT_ack_count_share0000_6_LOGIC_ZERO_3489,
      SEL => UUT_ack_count_share0000_6_CYSELF_3495,
      O => UUT_ack_count_share0000_6_CYMUXF2_3490
    );
  UUT_ack_count_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_5_Q,
      O => UUT_ack_count_share0000_6_CYINIT_3508
    );
  UUT_ack_count_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_F,
      O => UUT_ack_count_share0000_6_CYSELF_3495
    );
  UUT_ack_count_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_XORG_3497,
      O => UUT_ack_count_share0000(7)
    );
  UUT_ack_count_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      I0 => UUT_Madd_ack_count_share0000_cy_6_Q,
      I1 => UUT_ack_count_share0000_6_G,
      O => UUT_ack_count_share0000_6_XORG_3497
    );
  UUT_ack_count_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_CYMUXFAST_3494,
      O => UUT_Madd_ack_count_share0000_cy_7_Q
    );
  UUT_ack_count_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_ack_count_share0000_cy_5_Q,
      O => UUT_ack_count_share0000_6_FASTCARRY_3492
    );
  UUT_ack_count_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      I0 => UUT_ack_count_share0000_6_CYSELG_3480,
      I1 => UUT_ack_count_share0000_6_CYSELF_3495,
      O => UUT_ack_count_share0000_6_CYAND_3493
    );
  UUT_ack_count_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      IA => UUT_ack_count_share0000_6_CYMUXG2_3491,
      IB => UUT_ack_count_share0000_6_FASTCARRY_3492,
      SEL => UUT_ack_count_share0000_6_CYAND_3493,
      O => UUT_ack_count_share0000_6_CYMUXFAST_3494
    );
  UUT_ack_count_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y59"
    )
    port map (
      IA => UUT_ack_count_share0000_6_LOGIC_ZERO_3489,
      IB => UUT_ack_count_share0000_6_CYMUXF2_3490,
      SEL => UUT_ack_count_share0000_6_CYSELG_3480,
      O => UUT_ack_count_share0000_6_CYMUXG2_3491
    );
  UUT_ack_count_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_share0000_6_G,
      O => UUT_ack_count_share0000_6_CYSELG_3480
    );
  UUT_writeCount_share0000_12_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      O => UUT_writeCount_share0000_12_LOGIC_ZERO_2913
    );
  UUT_writeCount_share0000_12_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_XORF_2933,
      O => UUT_writeCount_share0000(12)
    );
  UUT_writeCount_share0000_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      I0 => UUT_writeCount_share0000_12_CYINIT_2932,
      I1 => UUT_writeCount_share0000_12_F,
      O => UUT_writeCount_share0000_12_XORF_2933
    );
  UUT_writeCount_share0000_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_LOGIC_ZERO_2913,
      IB => UUT_writeCount_share0000_12_CYINIT_2932,
      SEL => UUT_writeCount_share0000_12_CYSELF_2919,
      O => UUT_Madd_writeCount_share0000_cy(12)
    );
  UUT_writeCount_share0000_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_LOGIC_ZERO_2913,
      IB => UUT_writeCount_share0000_12_LOGIC_ZERO_2913,
      SEL => UUT_writeCount_share0000_12_CYSELF_2919,
      O => UUT_writeCount_share0000_12_CYMUXF2_2914
    );
  UUT_writeCount_share0000_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(11),
      O => UUT_writeCount_share0000_12_CYINIT_2932
    );
  UUT_writeCount_share0000_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_F,
      O => UUT_writeCount_share0000_12_CYSELF_2919
    );
  UUT_writeCount_share0000_12_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_XORG_2921,
      O => UUT_writeCount_share0000(13)
    );
  UUT_writeCount_share0000_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(12),
      I1 => UUT_writeCount_share0000_12_G,
      O => UUT_writeCount_share0000_12_XORG_2921
    );
  UUT_writeCount_share0000_12_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_CYMUXFAST_2918,
      O => UUT_Madd_writeCount_share0000_cy(13)
    );
  UUT_writeCount_share0000_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(11),
      O => UUT_writeCount_share0000_12_FASTCARRY_2916
    );
  UUT_writeCount_share0000_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      I0 => UUT_writeCount_share0000_12_CYSELG_2904,
      I1 => UUT_writeCount_share0000_12_CYSELF_2919,
      O => UUT_writeCount_share0000_12_CYAND_2917
    );
  UUT_writeCount_share0000_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_CYMUXG2_2915,
      IB => UUT_writeCount_share0000_12_FASTCARRY_2916,
      SEL => UUT_writeCount_share0000_12_CYAND_2917,
      O => UUT_writeCount_share0000_12_CYMUXFAST_2918
    );
  UUT_writeCount_share0000_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y6"
    )
    port map (
      IA => UUT_writeCount_share0000_12_LOGIC_ZERO_2913,
      IB => UUT_writeCount_share0000_12_CYMUXF2_2914,
      SEL => UUT_writeCount_share0000_12_CYSELG_2904,
      O => UUT_writeCount_share0000_12_CYMUXG2_2915
    );
  UUT_writeCount_share0000_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_12_G,
      O => UUT_writeCount_share0000_12_CYSELG_2904
    );
  UUT_writeCount_share0000_14_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      O => UUT_writeCount_share0000_14_LOGIC_ZERO_2951
    );
  UUT_writeCount_share0000_14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_XORF_2971,
      O => UUT_writeCount_share0000(14)
    );
  UUT_writeCount_share0000_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      I0 => UUT_writeCount_share0000_14_CYINIT_2970,
      I1 => UUT_writeCount_share0000_14_F,
      O => UUT_writeCount_share0000_14_XORF_2971
    );
  UUT_writeCount_share0000_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_LOGIC_ZERO_2951,
      IB => UUT_writeCount_share0000_14_CYINIT_2970,
      SEL => UUT_writeCount_share0000_14_CYSELF_2957,
      O => UUT_Madd_writeCount_share0000_cy(14)
    );
  UUT_writeCount_share0000_14_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_LOGIC_ZERO_2951,
      IB => UUT_writeCount_share0000_14_LOGIC_ZERO_2951,
      SEL => UUT_writeCount_share0000_14_CYSELF_2957,
      O => UUT_writeCount_share0000_14_CYMUXF2_2952
    );
  UUT_writeCount_share0000_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(13),
      O => UUT_writeCount_share0000_14_CYINIT_2970
    );
  UUT_writeCount_share0000_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_F,
      O => UUT_writeCount_share0000_14_CYSELF_2957
    );
  UUT_writeCount_share0000_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_XORG_2959,
      O => UUT_writeCount_share0000(15)
    );
  UUT_writeCount_share0000_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(14),
      I1 => UUT_writeCount_share0000_14_G,
      O => UUT_writeCount_share0000_14_XORG_2959
    );
  UUT_writeCount_share0000_14_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_CYMUXFAST_2956,
      O => UUT_Madd_writeCount_share0000_cy(15)
    );
  UUT_writeCount_share0000_14_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(13),
      O => UUT_writeCount_share0000_14_FASTCARRY_2954
    );
  UUT_writeCount_share0000_14_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      I0 => UUT_writeCount_share0000_14_CYSELG_2942,
      I1 => UUT_writeCount_share0000_14_CYSELF_2957,
      O => UUT_writeCount_share0000_14_CYAND_2955
    );
  UUT_writeCount_share0000_14_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_CYMUXG2_2953,
      IB => UUT_writeCount_share0000_14_FASTCARRY_2954,
      SEL => UUT_writeCount_share0000_14_CYAND_2955,
      O => UUT_writeCount_share0000_14_CYMUXFAST_2956
    );
  UUT_writeCount_share0000_14_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y7"
    )
    port map (
      IA => UUT_writeCount_share0000_14_LOGIC_ZERO_2951,
      IB => UUT_writeCount_share0000_14_CYMUXF2_2952,
      SEL => UUT_writeCount_share0000_14_CYSELG_2942,
      O => UUT_writeCount_share0000_14_CYMUXG2_2953
    );
  UUT_writeCount_share0000_14_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_14_G,
      O => UUT_writeCount_share0000_14_CYSELG_2942
    );
  UUT_writeCount_share0000_16_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      O => UUT_writeCount_share0000_16_LOGIC_ZERO_2989
    );
  UUT_writeCount_share0000_16_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_XORF_3009,
      O => UUT_writeCount_share0000(16)
    );
  UUT_writeCount_share0000_16_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      I0 => UUT_writeCount_share0000_16_CYINIT_3008,
      I1 => UUT_writeCount_share0000_16_F,
      O => UUT_writeCount_share0000_16_XORF_3009
    );
  UUT_writeCount_share0000_16_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_LOGIC_ZERO_2989,
      IB => UUT_writeCount_share0000_16_CYINIT_3008,
      SEL => UUT_writeCount_share0000_16_CYSELF_2995,
      O => UUT_Madd_writeCount_share0000_cy(16)
    );
  UUT_writeCount_share0000_16_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_LOGIC_ZERO_2989,
      IB => UUT_writeCount_share0000_16_LOGIC_ZERO_2989,
      SEL => UUT_writeCount_share0000_16_CYSELF_2995,
      O => UUT_writeCount_share0000_16_CYMUXF2_2990
    );
  UUT_writeCount_share0000_16_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(15),
      O => UUT_writeCount_share0000_16_CYINIT_3008
    );
  UUT_writeCount_share0000_16_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_F,
      O => UUT_writeCount_share0000_16_CYSELF_2995
    );
  UUT_writeCount_share0000_16_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_XORG_2997,
      O => UUT_writeCount_share0000(17)
    );
  UUT_writeCount_share0000_16_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(16),
      I1 => UUT_writeCount_share0000_16_G,
      O => UUT_writeCount_share0000_16_XORG_2997
    );
  UUT_writeCount_share0000_16_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_CYMUXFAST_2994,
      O => UUT_Madd_writeCount_share0000_cy(17)
    );
  UUT_writeCount_share0000_16_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(15),
      O => UUT_writeCount_share0000_16_FASTCARRY_2992
    );
  UUT_writeCount_share0000_16_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      I0 => UUT_writeCount_share0000_16_CYSELG_2980,
      I1 => UUT_writeCount_share0000_16_CYSELF_2995,
      O => UUT_writeCount_share0000_16_CYAND_2993
    );
  UUT_writeCount_share0000_16_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_CYMUXG2_2991,
      IB => UUT_writeCount_share0000_16_FASTCARRY_2992,
      SEL => UUT_writeCount_share0000_16_CYAND_2993,
      O => UUT_writeCount_share0000_16_CYMUXFAST_2994
    );
  UUT_writeCount_share0000_16_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y8"
    )
    port map (
      IA => UUT_writeCount_share0000_16_LOGIC_ZERO_2989,
      IB => UUT_writeCount_share0000_16_CYMUXF2_2990,
      SEL => UUT_writeCount_share0000_16_CYSELG_2980,
      O => UUT_writeCount_share0000_16_CYMUXG2_2991
    );
  UUT_writeCount_share0000_16_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_16_G,
      O => UUT_writeCount_share0000_16_CYSELG_2980
    );
  UUT_writeCount_share0000_18_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      O => UUT_writeCount_share0000_18_LOGIC_ZERO_3027
    );
  UUT_writeCount_share0000_18_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_XORF_3047,
      O => UUT_writeCount_share0000(18)
    );
  UUT_writeCount_share0000_18_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      I0 => UUT_writeCount_share0000_18_CYINIT_3046,
      I1 => UUT_writeCount_share0000_18_F,
      O => UUT_writeCount_share0000_18_XORF_3047
    );
  UUT_writeCount_share0000_18_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_LOGIC_ZERO_3027,
      IB => UUT_writeCount_share0000_18_CYINIT_3046,
      SEL => UUT_writeCount_share0000_18_CYSELF_3033,
      O => UUT_Madd_writeCount_share0000_cy(18)
    );
  UUT_writeCount_share0000_18_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_LOGIC_ZERO_3027,
      IB => UUT_writeCount_share0000_18_LOGIC_ZERO_3027,
      SEL => UUT_writeCount_share0000_18_CYSELF_3033,
      O => UUT_writeCount_share0000_18_CYMUXF2_3028
    );
  UUT_writeCount_share0000_18_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(17),
      O => UUT_writeCount_share0000_18_CYINIT_3046
    );
  UUT_writeCount_share0000_18_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_F,
      O => UUT_writeCount_share0000_18_CYSELF_3033
    );
  UUT_writeCount_share0000_18_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_XORG_3035,
      O => UUT_writeCount_share0000(19)
    );
  UUT_writeCount_share0000_18_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(18),
      I1 => UUT_writeCount_share0000_18_G,
      O => UUT_writeCount_share0000_18_XORG_3035
    );
  UUT_writeCount_share0000_18_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_CYMUXFAST_3032,
      O => UUT_Madd_writeCount_share0000_cy(19)
    );
  UUT_writeCount_share0000_18_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(17),
      O => UUT_writeCount_share0000_18_FASTCARRY_3030
    );
  UUT_writeCount_share0000_18_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      I0 => UUT_writeCount_share0000_18_CYSELG_3018,
      I1 => UUT_writeCount_share0000_18_CYSELF_3033,
      O => UUT_writeCount_share0000_18_CYAND_3031
    );
  UUT_writeCount_share0000_18_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_CYMUXG2_3029,
      IB => UUT_writeCount_share0000_18_FASTCARRY_3030,
      SEL => UUT_writeCount_share0000_18_CYAND_3031,
      O => UUT_writeCount_share0000_18_CYMUXFAST_3032
    );
  UUT_writeCount_share0000_18_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y9"
    )
    port map (
      IA => UUT_writeCount_share0000_18_LOGIC_ZERO_3027,
      IB => UUT_writeCount_share0000_18_CYMUXF2_3028,
      SEL => UUT_writeCount_share0000_18_CYSELG_3018,
      O => UUT_writeCount_share0000_18_CYMUXG2_3029
    );
  UUT_writeCount_share0000_18_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_18_G,
      O => UUT_writeCount_share0000_18_CYSELG_3018
    );
  UUT_writeCount_share0000_20_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      O => UUT_writeCount_share0000_20_LOGIC_ZERO_3065
    );
  UUT_writeCount_share0000_20_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_XORF_3085,
      O => UUT_writeCount_share0000(20)
    );
  UUT_writeCount_share0000_20_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      I0 => UUT_writeCount_share0000_20_CYINIT_3084,
      I1 => UUT_writeCount_share0000_20_F,
      O => UUT_writeCount_share0000_20_XORF_3085
    );
  UUT_writeCount_share0000_20_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_LOGIC_ZERO_3065,
      IB => UUT_writeCount_share0000_20_CYINIT_3084,
      SEL => UUT_writeCount_share0000_20_CYSELF_3071,
      O => UUT_Madd_writeCount_share0000_cy(20)
    );
  UUT_writeCount_share0000_20_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_LOGIC_ZERO_3065,
      IB => UUT_writeCount_share0000_20_LOGIC_ZERO_3065,
      SEL => UUT_writeCount_share0000_20_CYSELF_3071,
      O => UUT_writeCount_share0000_20_CYMUXF2_3066
    );
  UUT_writeCount_share0000_20_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(19),
      O => UUT_writeCount_share0000_20_CYINIT_3084
    );
  UUT_writeCount_share0000_20_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_F,
      O => UUT_writeCount_share0000_20_CYSELF_3071
    );
  UUT_writeCount_share0000_20_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_XORG_3073,
      O => UUT_writeCount_share0000(21)
    );
  UUT_writeCount_share0000_20_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(20),
      I1 => UUT_writeCount_share0000_20_G,
      O => UUT_writeCount_share0000_20_XORG_3073
    );
  UUT_writeCount_share0000_20_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_CYMUXFAST_3070,
      O => UUT_Madd_writeCount_share0000_cy(21)
    );
  UUT_writeCount_share0000_20_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(19),
      O => UUT_writeCount_share0000_20_FASTCARRY_3068
    );
  UUT_writeCount_share0000_20_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      I0 => UUT_writeCount_share0000_20_CYSELG_3056,
      I1 => UUT_writeCount_share0000_20_CYSELF_3071,
      O => UUT_writeCount_share0000_20_CYAND_3069
    );
  UUT_writeCount_share0000_20_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_CYMUXG2_3067,
      IB => UUT_writeCount_share0000_20_FASTCARRY_3068,
      SEL => UUT_writeCount_share0000_20_CYAND_3069,
      O => UUT_writeCount_share0000_20_CYMUXFAST_3070
    );
  UUT_writeCount_share0000_20_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y10"
    )
    port map (
      IA => UUT_writeCount_share0000_20_LOGIC_ZERO_3065,
      IB => UUT_writeCount_share0000_20_CYMUXF2_3066,
      SEL => UUT_writeCount_share0000_20_CYSELG_3056,
      O => UUT_writeCount_share0000_20_CYMUXG2_3067
    );
  UUT_writeCount_share0000_20_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_20_G,
      O => UUT_writeCount_share0000_20_CYSELG_3056
    );
  UUT_writeCount_share0000_22_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      O => UUT_writeCount_share0000_22_LOGIC_ZERO_3103
    );
  UUT_writeCount_share0000_22_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_XORF_3123,
      O => UUT_writeCount_share0000(22)
    );
  UUT_writeCount_share0000_22_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      I0 => UUT_writeCount_share0000_22_CYINIT_3122,
      I1 => UUT_writeCount_share0000_22_F,
      O => UUT_writeCount_share0000_22_XORF_3123
    );
  UUT_writeCount_share0000_22_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_LOGIC_ZERO_3103,
      IB => UUT_writeCount_share0000_22_CYINIT_3122,
      SEL => UUT_writeCount_share0000_22_CYSELF_3109,
      O => UUT_Madd_writeCount_share0000_cy(22)
    );
  UUT_writeCount_share0000_22_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_LOGIC_ZERO_3103,
      IB => UUT_writeCount_share0000_22_LOGIC_ZERO_3103,
      SEL => UUT_writeCount_share0000_22_CYSELF_3109,
      O => UUT_writeCount_share0000_22_CYMUXF2_3104
    );
  UUT_writeCount_share0000_22_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(21),
      O => UUT_writeCount_share0000_22_CYINIT_3122
    );
  UUT_writeCount_share0000_22_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_F,
      O => UUT_writeCount_share0000_22_CYSELF_3109
    );
  UUT_writeCount_share0000_22_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_XORG_3111,
      O => UUT_writeCount_share0000(23)
    );
  UUT_writeCount_share0000_22_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(22),
      I1 => UUT_writeCount_share0000_22_G,
      O => UUT_writeCount_share0000_22_XORG_3111
    );
  UUT_writeCount_share0000_22_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_CYMUXFAST_3108,
      O => UUT_Madd_writeCount_share0000_cy(23)
    );
  UUT_writeCount_share0000_22_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(21),
      O => UUT_writeCount_share0000_22_FASTCARRY_3106
    );
  UUT_writeCount_share0000_22_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      I0 => UUT_writeCount_share0000_22_CYSELG_3094,
      I1 => UUT_writeCount_share0000_22_CYSELF_3109,
      O => UUT_writeCount_share0000_22_CYAND_3107
    );
  UUT_writeCount_share0000_22_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_CYMUXG2_3105,
      IB => UUT_writeCount_share0000_22_FASTCARRY_3106,
      SEL => UUT_writeCount_share0000_22_CYAND_3107,
      O => UUT_writeCount_share0000_22_CYMUXFAST_3108
    );
  UUT_writeCount_share0000_22_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y11"
    )
    port map (
      IA => UUT_writeCount_share0000_22_LOGIC_ZERO_3103,
      IB => UUT_writeCount_share0000_22_CYMUXF2_3104,
      SEL => UUT_writeCount_share0000_22_CYSELG_3094,
      O => UUT_writeCount_share0000_22_CYMUXG2_3105
    );
  UUT_writeCount_share0000_22_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_22_G,
      O => UUT_writeCount_share0000_22_CYSELG_3094
    );
  UUT_writeCount_share0000_24_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      O => UUT_writeCount_share0000_24_LOGIC_ZERO_3141
    );
  UUT_writeCount_share0000_24_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_XORF_3161,
      O => UUT_writeCount_share0000(24)
    );
  UUT_writeCount_share0000_24_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      I0 => UUT_writeCount_share0000_24_CYINIT_3160,
      I1 => UUT_writeCount_share0000_24_F,
      O => UUT_writeCount_share0000_24_XORF_3161
    );
  UUT_writeCount_share0000_24_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_LOGIC_ZERO_3141,
      IB => UUT_writeCount_share0000_24_CYINIT_3160,
      SEL => UUT_writeCount_share0000_24_CYSELF_3147,
      O => UUT_Madd_writeCount_share0000_cy(24)
    );
  UUT_writeCount_share0000_24_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_LOGIC_ZERO_3141,
      IB => UUT_writeCount_share0000_24_LOGIC_ZERO_3141,
      SEL => UUT_writeCount_share0000_24_CYSELF_3147,
      O => UUT_writeCount_share0000_24_CYMUXF2_3142
    );
  UUT_writeCount_share0000_24_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(23),
      O => UUT_writeCount_share0000_24_CYINIT_3160
    );
  UUT_writeCount_share0000_24_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_F,
      O => UUT_writeCount_share0000_24_CYSELF_3147
    );
  UUT_writeCount_share0000_24_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_XORG_3149,
      O => UUT_writeCount_share0000(25)
    );
  UUT_writeCount_share0000_24_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(24),
      I1 => UUT_writeCount_share0000_24_G,
      O => UUT_writeCount_share0000_24_XORG_3149
    );
  UUT_writeCount_share0000_24_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_CYMUXFAST_3146,
      O => UUT_Madd_writeCount_share0000_cy(25)
    );
  UUT_writeCount_share0000_24_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(23),
      O => UUT_writeCount_share0000_24_FASTCARRY_3144
    );
  UUT_writeCount_share0000_24_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      I0 => UUT_writeCount_share0000_24_CYSELG_3132,
      I1 => UUT_writeCount_share0000_24_CYSELF_3147,
      O => UUT_writeCount_share0000_24_CYAND_3145
    );
  UUT_writeCount_share0000_24_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_CYMUXG2_3143,
      IB => UUT_writeCount_share0000_24_FASTCARRY_3144,
      SEL => UUT_writeCount_share0000_24_CYAND_3145,
      O => UUT_writeCount_share0000_24_CYMUXFAST_3146
    );
  UUT_writeCount_share0000_24_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y12"
    )
    port map (
      IA => UUT_writeCount_share0000_24_LOGIC_ZERO_3141,
      IB => UUT_writeCount_share0000_24_CYMUXF2_3142,
      SEL => UUT_writeCount_share0000_24_CYSELG_3132,
      O => UUT_writeCount_share0000_24_CYMUXG2_3143
    );
  UUT_writeCount_share0000_24_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_24_G,
      O => UUT_writeCount_share0000_24_CYSELG_3132
    );
  UUT_writeCount_share0000_26_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      O => UUT_writeCount_share0000_26_LOGIC_ZERO_3179
    );
  UUT_writeCount_share0000_26_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_XORF_3199,
      O => UUT_writeCount_share0000(26)
    );
  UUT_writeCount_share0000_26_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      I0 => UUT_writeCount_share0000_26_CYINIT_3198,
      I1 => UUT_writeCount_share0000_26_F,
      O => UUT_writeCount_share0000_26_XORF_3199
    );
  UUT_writeCount_share0000_26_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_LOGIC_ZERO_3179,
      IB => UUT_writeCount_share0000_26_CYINIT_3198,
      SEL => UUT_writeCount_share0000_26_CYSELF_3185,
      O => UUT_Madd_writeCount_share0000_cy(26)
    );
  UUT_writeCount_share0000_26_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_LOGIC_ZERO_3179,
      IB => UUT_writeCount_share0000_26_LOGIC_ZERO_3179,
      SEL => UUT_writeCount_share0000_26_CYSELF_3185,
      O => UUT_writeCount_share0000_26_CYMUXF2_3180
    );
  UUT_writeCount_share0000_26_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(25),
      O => UUT_writeCount_share0000_26_CYINIT_3198
    );
  UUT_writeCount_share0000_26_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_F,
      O => UUT_writeCount_share0000_26_CYSELF_3185
    );
  UUT_writeCount_share0000_26_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_XORG_3187,
      O => UUT_writeCount_share0000(27)
    );
  UUT_writeCount_share0000_26_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      I0 => UUT_Madd_writeCount_share0000_cy(26),
      I1 => UUT_writeCount_share0000_26_G,
      O => UUT_writeCount_share0000_26_XORG_3187
    );
  UUT_writeCount_share0000_26_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_CYMUXFAST_3184,
      O => UUT_Madd_writeCount_share0000_cy(27)
    );
  UUT_writeCount_share0000_26_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_writeCount_share0000_cy(25),
      O => UUT_writeCount_share0000_26_FASTCARRY_3182
    );
  UUT_writeCount_share0000_26_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      I0 => UUT_writeCount_share0000_26_CYSELG_3170,
      I1 => UUT_writeCount_share0000_26_CYSELF_3185,
      O => UUT_writeCount_share0000_26_CYAND_3183
    );
  UUT_writeCount_share0000_26_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_CYMUXG2_3181,
      IB => UUT_writeCount_share0000_26_FASTCARRY_3182,
      SEL => UUT_writeCount_share0000_26_CYAND_3183,
      O => UUT_writeCount_share0000_26_CYMUXFAST_3184
    );
  UUT_writeCount_share0000_26_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X17Y13"
    )
    port map (
      IA => UUT_writeCount_share0000_26_LOGIC_ZERO_3179,
      IB => UUT_writeCount_share0000_26_CYMUXF2_3180,
      SEL => UUT_writeCount_share0000_26_CYSELG_3170,
      O => UUT_writeCount_share0000_26_CYMUXG2_3181
    );
  UUT_writeCount_share0000_26_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X17Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_share0000_26_G,
      O => UUT_writeCount_share0000_26_CYSELG_3170
    );
  CLK_clk_div_2_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      O => CLK_clk_div_2_LOGIC_ZERO_4212
    );
  CLK_clk_div_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_XORF_4237,
      O => CLK_clk_div_2_DXMUX_4239
    );
  CLK_clk_div_2_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      I0 => CLK_clk_div_2_CYINIT_4236,
      I1 => CLK_clk_div_2_F,
      O => CLK_clk_div_2_XORF_4237
    );
  CLK_clk_div_2_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      IA => CLK_clk_div_2_LOGIC_ZERO_4212,
      IB => CLK_clk_div_2_CYINIT_4236,
      SEL => CLK_clk_div_2_CYSELF_4218,
      O => CLK_Mcount_clk_div_cy_2_Q
    );
  CLK_clk_div_2_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      IA => CLK_clk_div_2_LOGIC_ZERO_4212,
      IB => CLK_clk_div_2_LOGIC_ZERO_4212,
      SEL => CLK_clk_div_2_CYSELF_4218,
      O => CLK_clk_div_2_CYMUXF2_4213
    );
  CLK_clk_div_2_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_1_Q,
      O => CLK_clk_div_2_CYINIT_4236
    );
  CLK_clk_div_2_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_F,
      O => CLK_clk_div_2_CYSELF_4218
    );
  CLK_clk_div_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_XORG_4220,
      O => CLK_clk_div_2_DYMUX_4222
    );
  CLK_clk_div_2_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_2_Q,
      I1 => CLK_clk_div_2_G,
      O => CLK_clk_div_2_XORG_4220
    );
  CLK_clk_div_2_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_CYMUXFAST_4217,
      O => CLK_Mcount_clk_div_cy_3_Q
    );
  CLK_clk_div_2_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_1_Q,
      O => CLK_clk_div_2_FASTCARRY_4215
    );
  CLK_clk_div_2_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      I0 => CLK_clk_div_2_CYSELG_4203,
      I1 => CLK_clk_div_2_CYSELF_4218,
      O => CLK_clk_div_2_CYAND_4216
    );
  CLK_clk_div_2_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      IA => CLK_clk_div_2_CYMUXG2_4214,
      IB => CLK_clk_div_2_FASTCARRY_4215,
      SEL => CLK_clk_div_2_CYAND_4216,
      O => CLK_clk_div_2_CYMUXFAST_4217
    );
  CLK_clk_div_2_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y36"
    )
    port map (
      IA => CLK_clk_div_2_LOGIC_ZERO_4212,
      IB => CLK_clk_div_2_CYMUXF2_4213,
      SEL => CLK_clk_div_2_CYSELG_4203,
      O => CLK_clk_div_2_CYMUXG2_4214
    );
  CLK_clk_div_2_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_2_G,
      O => CLK_clk_div_2_CYSELG_4203
    );
  CLK_clk_div_2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_2_SRINV_4201
    );
  CLK_clk_div_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_2_CLKINV_4200
    );
  CLK_clk_div_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      O => CLK_clk_div_4_LOGIC_ZERO_4264
    );
  CLK_clk_div_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_XORF_4289,
      O => CLK_clk_div_4_DXMUX_4291
    );
  CLK_clk_div_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      I0 => CLK_clk_div_4_CYINIT_4288,
      I1 => CLK_clk_div_4_F,
      O => CLK_clk_div_4_XORF_4289
    );
  CLK_clk_div_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      IA => CLK_clk_div_4_LOGIC_ZERO_4264,
      IB => CLK_clk_div_4_CYINIT_4288,
      SEL => CLK_clk_div_4_CYSELF_4270,
      O => CLK_Mcount_clk_div_cy_4_Q
    );
  CLK_clk_div_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      IA => CLK_clk_div_4_LOGIC_ZERO_4264,
      IB => CLK_clk_div_4_LOGIC_ZERO_4264,
      SEL => CLK_clk_div_4_CYSELF_4270,
      O => CLK_clk_div_4_CYMUXF2_4265
    );
  CLK_clk_div_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_3_Q,
      O => CLK_clk_div_4_CYINIT_4288
    );
  CLK_clk_div_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_F,
      O => CLK_clk_div_4_CYSELF_4270
    );
  CLK_clk_div_4_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_XORG_4272,
      O => CLK_clk_div_4_DYMUX_4274
    );
  CLK_clk_div_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_4_Q,
      I1 => CLK_clk_div_4_G,
      O => CLK_clk_div_4_XORG_4272
    );
  CLK_clk_div_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_cy_3_Q,
      O => CLK_clk_div_4_FASTCARRY_4267
    );
  CLK_clk_div_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      I0 => CLK_clk_div_4_CYSELG_4255,
      I1 => CLK_clk_div_4_CYSELF_4270,
      O => CLK_clk_div_4_CYAND_4268
    );
  CLK_clk_div_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      IA => CLK_clk_div_4_CYMUXG2_4266,
      IB => CLK_clk_div_4_FASTCARRY_4267,
      SEL => CLK_clk_div_4_CYAND_4268,
      O => CLK_clk_div_4_CYMUXFAST_4269
    );
  CLK_clk_div_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X29Y37"
    )
    port map (
      IA => CLK_clk_div_4_LOGIC_ZERO_4264,
      IB => CLK_clk_div_4_CYMUXF2_4265,
      SEL => CLK_clk_div_4_CYSELG_4255,
      O => CLK_clk_div_4_CYMUXG2_4266
    );
  CLK_clk_div_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_G,
      O => CLK_clk_div_4_CYSELG_4255
    );
  CLK_clk_div_4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_4_SRINV_4253
    );
  CLK_clk_div_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_4_CLKINV_4252
    );
  CLK_clk_div_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X29Y38"
    )
    port map (
      O => CLK_clk_div_6_LOGIC_ZERO_4333
    );
  CLK_clk_div_6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_6_XORF_4334,
      O => CLK_clk_div_6_DXMUX_4336
    );
  CLK_clk_div_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X29Y38"
    )
    port map (
      I0 => CLK_clk_div_6_CYINIT_4332,
      I1 => CLK_clk_div_6_F,
      O => CLK_clk_div_6_XORF_4334
    );
  CLK_clk_div_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X29Y38"
    )
    port map (
      IA => CLK_clk_div_6_LOGIC_ZERO_4333,
      IB => CLK_clk_div_6_CYINIT_4332,
      SEL => CLK_clk_div_6_CYSELF_4323,
      O => CLK_Mcount_clk_div_cy_6_Q
    );
  CLK_clk_div_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X29Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_4_CYMUXFAST_4269,
      O => CLK_clk_div_6_CYINIT_4332
    );
  CLK_clk_div_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_6_F,
      O => CLK_clk_div_6_CYSELF_4323
    );
  CLK_clk_div_6_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_6_XORG_4315,
      O => CLK_clk_div_6_DYMUX_4317
    );
  CLK_clk_div_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X29Y38"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_6_Q,
      I1 => CLK_clk_div_7_rt_4312,
      O => CLK_clk_div_6_XORG_4315
    );
  CLK_clk_div_6_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_6_SRINV_4304
    );
  CLK_clk_div_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_6_CLKINV_4303
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X35Y19"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE_4356
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y19"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO_4370
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X35Y19"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ZERO_4370,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT_4369,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF_4361,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_0_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X35Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYINIT_4369
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_4360,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELF_4361
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X35Y19"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_LOGIC_ONE_4356,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_0_1,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG_4347,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG_4358
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_4_rt,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYSELG_4347
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE_4385
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4401
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4401,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ZERO_4401,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4391,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2_4386
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_2_1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4391
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_1_1_CYMUXG_4358,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY_4388
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4377,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELF_4391,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND_4389
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2_4387,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_FASTCARRY_4388,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYAND_4389,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST_4390
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y20"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_LOGIC_ONE_4385,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXF2_4386,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4377,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXG2_4387
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(3),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYSELG_4377
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE_4416
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4432
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4432,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ZERO_4432,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4422,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2_4417
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_4_1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4422
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_3_1_CYMUXFAST_4390,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY_4419
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4408,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELF_4422,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND_4420
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2_4418,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_FASTCARRY_4419,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYAND_4420,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST_4421
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y21"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_LOGIC_ONE_4416,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXF2_4417,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4408,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXG2_4418
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_4407,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYSELG_4408
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4450
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4450,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4450,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4456,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2_4451
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(6),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4456
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST_4455,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_5_1_CYMUXFAST_4421,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY_4453
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4441,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELF_4456,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND_4454
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2_4452,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_7_FASTCARRY_4453,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYAND_4454,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXFAST_4455
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X35Y22"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_7_LOGIC_ZERO_4450,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXF2_4451,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4441,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYMUXG2_4452
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X35Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_7_CYSELG_4441
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y17"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE_4479
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y17"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO_4492
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X31Y17"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ZERO_4492,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT_4491,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF_4484,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X31Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYINIT_4491
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(0),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELF_4484
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X31Y17"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_1_LOGIC_ONE_4479,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_0_Q,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG_4471,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG_4481
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(1),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYSELG_4471
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X31Y18"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE_4507
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y18"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4523
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y18"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4523,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ZERO_4523,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4513,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2_4508
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(2),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4513
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X31Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_1_CYMUXG_4481,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY_4510
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X31Y18"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4498,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELF_4513,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND_4511
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X31Y18"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2_4509,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_FASTCARRY_4510,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYAND_4511,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST_4512
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y18"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_3_LOGIC_ONE_4507,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXF2_4508,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4498,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXG2_4509
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_3_G,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYSELG_4498
    );
  UUT_delay_count_share0000_4_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      O => UUT_delay_count_share0000_4_LOGIC_ZERO_3849
    );
  UUT_delay_count_share0000_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_XORF_3869,
      O => UUT_delay_count_share0000(4)
    );
  UUT_delay_count_share0000_4_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      I0 => UUT_delay_count_share0000_4_CYINIT_3868,
      I1 => UUT_delay_count_share0000_4_F,
      O => UUT_delay_count_share0000_4_XORF_3869
    );
  UUT_delay_count_share0000_4_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      IA => UUT_delay_count_share0000_4_LOGIC_ZERO_3849,
      IB => UUT_delay_count_share0000_4_CYINIT_3868,
      SEL => UUT_delay_count_share0000_4_CYSELF_3855,
      O => UUT_Madd_delay_count_share0000_cy_4_Q
    );
  UUT_delay_count_share0000_4_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      IA => UUT_delay_count_share0000_4_LOGIC_ZERO_3849,
      IB => UUT_delay_count_share0000_4_LOGIC_ZERO_3849,
      SEL => UUT_delay_count_share0000_4_CYSELF_3855,
      O => UUT_delay_count_share0000_4_CYMUXF2_3850
    );
  UUT_delay_count_share0000_4_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_3_Q,
      O => UUT_delay_count_share0000_4_CYINIT_3868
    );
  UUT_delay_count_share0000_4_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_F,
      O => UUT_delay_count_share0000_4_CYSELF_3855
    );
  UUT_delay_count_share0000_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_XORG_3857,
      O => UUT_delay_count_share0000(5)
    );
  UUT_delay_count_share0000_4_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_4_Q,
      I1 => UUT_delay_count_share0000_4_G,
      O => UUT_delay_count_share0000_4_XORG_3857
    );
  UUT_delay_count_share0000_4_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_CYMUXFAST_3854,
      O => UUT_Madd_delay_count_share0000_cy_5_Q
    );
  UUT_delay_count_share0000_4_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_3_Q,
      O => UUT_delay_count_share0000_4_FASTCARRY_3852
    );
  UUT_delay_count_share0000_4_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      I0 => UUT_delay_count_share0000_4_CYSELG_3840,
      I1 => UUT_delay_count_share0000_4_CYSELF_3855,
      O => UUT_delay_count_share0000_4_CYAND_3853
    );
  UUT_delay_count_share0000_4_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      IA => UUT_delay_count_share0000_4_CYMUXG2_3851,
      IB => UUT_delay_count_share0000_4_FASTCARRY_3852,
      SEL => UUT_delay_count_share0000_4_CYAND_3853,
      O => UUT_delay_count_share0000_4_CYMUXFAST_3854
    );
  UUT_delay_count_share0000_4_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y17"
    )
    port map (
      IA => UUT_delay_count_share0000_4_LOGIC_ZERO_3849,
      IB => UUT_delay_count_share0000_4_CYMUXF2_3850,
      SEL => UUT_delay_count_share0000_4_CYSELG_3840,
      O => UUT_delay_count_share0000_4_CYMUXG2_3851
    );
  UUT_delay_count_share0000_4_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_4_G,
      O => UUT_delay_count_share0000_4_CYSELG_3840
    );
  UUT_delay_count_share0000_6_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      O => UUT_delay_count_share0000_6_LOGIC_ZERO_3887
    );
  UUT_delay_count_share0000_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_XORF_3907,
      O => UUT_delay_count_share0000(6)
    );
  UUT_delay_count_share0000_6_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      I0 => UUT_delay_count_share0000_6_CYINIT_3906,
      I1 => UUT_delay_count_share0000_6_F,
      O => UUT_delay_count_share0000_6_XORF_3907
    );
  UUT_delay_count_share0000_6_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      IA => UUT_delay_count_share0000_6_LOGIC_ZERO_3887,
      IB => UUT_delay_count_share0000_6_CYINIT_3906,
      SEL => UUT_delay_count_share0000_6_CYSELF_3893,
      O => UUT_Madd_delay_count_share0000_cy_6_Q
    );
  UUT_delay_count_share0000_6_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      IA => UUT_delay_count_share0000_6_LOGIC_ZERO_3887,
      IB => UUT_delay_count_share0000_6_LOGIC_ZERO_3887,
      SEL => UUT_delay_count_share0000_6_CYSELF_3893,
      O => UUT_delay_count_share0000_6_CYMUXF2_3888
    );
  UUT_delay_count_share0000_6_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_5_Q,
      O => UUT_delay_count_share0000_6_CYINIT_3906
    );
  UUT_delay_count_share0000_6_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_F,
      O => UUT_delay_count_share0000_6_CYSELF_3893
    );
  UUT_delay_count_share0000_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_XORG_3895,
      O => UUT_delay_count_share0000(7)
    );
  UUT_delay_count_share0000_6_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_6_Q,
      I1 => UUT_delay_count_share0000_6_G,
      O => UUT_delay_count_share0000_6_XORG_3895
    );
  UUT_delay_count_share0000_6_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_CYMUXFAST_3892,
      O => UUT_Madd_delay_count_share0000_cy_7_Q
    );
  UUT_delay_count_share0000_6_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_5_Q,
      O => UUT_delay_count_share0000_6_FASTCARRY_3890
    );
  UUT_delay_count_share0000_6_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      I0 => UUT_delay_count_share0000_6_CYSELG_3878,
      I1 => UUT_delay_count_share0000_6_CYSELF_3893,
      O => UUT_delay_count_share0000_6_CYAND_3891
    );
  UUT_delay_count_share0000_6_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      IA => UUT_delay_count_share0000_6_CYMUXG2_3889,
      IB => UUT_delay_count_share0000_6_FASTCARRY_3890,
      SEL => UUT_delay_count_share0000_6_CYAND_3891,
      O => UUT_delay_count_share0000_6_CYMUXFAST_3892
    );
  UUT_delay_count_share0000_6_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y18"
    )
    port map (
      IA => UUT_delay_count_share0000_6_LOGIC_ZERO_3887,
      IB => UUT_delay_count_share0000_6_CYMUXF2_3888,
      SEL => UUT_delay_count_share0000_6_CYSELG_3878,
      O => UUT_delay_count_share0000_6_CYMUXG2_3889
    );
  UUT_delay_count_share0000_6_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_6_G,
      O => UUT_delay_count_share0000_6_CYSELG_3878
    );
  UUT_delay_count_share0000_8_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      O => UUT_delay_count_share0000_8_LOGIC_ZERO_3925
    );
  UUT_delay_count_share0000_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_XORF_3945,
      O => UUT_delay_count_share0000(8)
    );
  UUT_delay_count_share0000_8_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      I0 => UUT_delay_count_share0000_8_CYINIT_3944,
      I1 => UUT_delay_count_share0000_8_F,
      O => UUT_delay_count_share0000_8_XORF_3945
    );
  UUT_delay_count_share0000_8_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      IA => UUT_delay_count_share0000_8_LOGIC_ZERO_3925,
      IB => UUT_delay_count_share0000_8_CYINIT_3944,
      SEL => UUT_delay_count_share0000_8_CYSELF_3931,
      O => UUT_Madd_delay_count_share0000_cy_8_Q
    );
  UUT_delay_count_share0000_8_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      IA => UUT_delay_count_share0000_8_LOGIC_ZERO_3925,
      IB => UUT_delay_count_share0000_8_LOGIC_ZERO_3925,
      SEL => UUT_delay_count_share0000_8_CYSELF_3931,
      O => UUT_delay_count_share0000_8_CYMUXF2_3926
    );
  UUT_delay_count_share0000_8_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_7_Q,
      O => UUT_delay_count_share0000_8_CYINIT_3944
    );
  UUT_delay_count_share0000_8_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_F,
      O => UUT_delay_count_share0000_8_CYSELF_3931
    );
  UUT_delay_count_share0000_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_XORG_3933,
      O => UUT_delay_count_share0000(9)
    );
  UUT_delay_count_share0000_8_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_8_Q,
      I1 => UUT_delay_count_share0000_8_G,
      O => UUT_delay_count_share0000_8_XORG_3933
    );
  UUT_delay_count_share0000_8_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_CYMUXFAST_3930,
      O => UUT_Madd_delay_count_share0000_cy_9_Q
    );
  UUT_delay_count_share0000_8_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_7_Q,
      O => UUT_delay_count_share0000_8_FASTCARRY_3928
    );
  UUT_delay_count_share0000_8_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      I0 => UUT_delay_count_share0000_8_CYSELG_3916,
      I1 => UUT_delay_count_share0000_8_CYSELF_3931,
      O => UUT_delay_count_share0000_8_CYAND_3929
    );
  UUT_delay_count_share0000_8_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      IA => UUT_delay_count_share0000_8_CYMUXG2_3927,
      IB => UUT_delay_count_share0000_8_FASTCARRY_3928,
      SEL => UUT_delay_count_share0000_8_CYAND_3929,
      O => UUT_delay_count_share0000_8_CYMUXFAST_3930
    );
  UUT_delay_count_share0000_8_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y19"
    )
    port map (
      IA => UUT_delay_count_share0000_8_LOGIC_ZERO_3925,
      IB => UUT_delay_count_share0000_8_CYMUXF2_3926,
      SEL => UUT_delay_count_share0000_8_CYSELG_3916,
      O => UUT_delay_count_share0000_8_CYMUXG2_3927
    );
  UUT_delay_count_share0000_8_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_8_G,
      O => UUT_delay_count_share0000_8_CYSELG_3916
    );
  UUT_delay_count_share0000_10_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      O => UUT_delay_count_share0000_10_LOGIC_ZERO_3963
    );
  UUT_delay_count_share0000_10_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_XORF_3983,
      O => UUT_delay_count_share0000(10)
    );
  UUT_delay_count_share0000_10_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      I0 => UUT_delay_count_share0000_10_CYINIT_3982,
      I1 => UUT_delay_count_share0000_10_F,
      O => UUT_delay_count_share0000_10_XORF_3983
    );
  UUT_delay_count_share0000_10_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      IA => UUT_delay_count_share0000_10_LOGIC_ZERO_3963,
      IB => UUT_delay_count_share0000_10_CYINIT_3982,
      SEL => UUT_delay_count_share0000_10_CYSELF_3969,
      O => UUT_Madd_delay_count_share0000_cy_10_Q
    );
  UUT_delay_count_share0000_10_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      IA => UUT_delay_count_share0000_10_LOGIC_ZERO_3963,
      IB => UUT_delay_count_share0000_10_LOGIC_ZERO_3963,
      SEL => UUT_delay_count_share0000_10_CYSELF_3969,
      O => UUT_delay_count_share0000_10_CYMUXF2_3964
    );
  UUT_delay_count_share0000_10_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_9_Q,
      O => UUT_delay_count_share0000_10_CYINIT_3982
    );
  UUT_delay_count_share0000_10_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_F,
      O => UUT_delay_count_share0000_10_CYSELF_3969
    );
  UUT_delay_count_share0000_10_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_XORG_3971,
      O => UUT_delay_count_share0000(11)
    );
  UUT_delay_count_share0000_10_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_10_Q,
      I1 => UUT_delay_count_share0000_10_G,
      O => UUT_delay_count_share0000_10_XORG_3971
    );
  UUT_delay_count_share0000_10_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_CYMUXFAST_3968,
      O => UUT_Madd_delay_count_share0000_cy_11_Q
    );
  UUT_delay_count_share0000_10_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_9_Q,
      O => UUT_delay_count_share0000_10_FASTCARRY_3966
    );
  UUT_delay_count_share0000_10_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      I0 => UUT_delay_count_share0000_10_CYSELG_3954,
      I1 => UUT_delay_count_share0000_10_CYSELF_3969,
      O => UUT_delay_count_share0000_10_CYAND_3967
    );
  UUT_delay_count_share0000_10_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      IA => UUT_delay_count_share0000_10_CYMUXG2_3965,
      IB => UUT_delay_count_share0000_10_FASTCARRY_3966,
      SEL => UUT_delay_count_share0000_10_CYAND_3967,
      O => UUT_delay_count_share0000_10_CYMUXFAST_3968
    );
  UUT_delay_count_share0000_10_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y20"
    )
    port map (
      IA => UUT_delay_count_share0000_10_LOGIC_ZERO_3963,
      IB => UUT_delay_count_share0000_10_CYMUXF2_3964,
      SEL => UUT_delay_count_share0000_10_CYSELG_3954,
      O => UUT_delay_count_share0000_10_CYMUXG2_3965
    );
  UUT_delay_count_share0000_10_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_10_G,
      O => UUT_delay_count_share0000_10_CYSELG_3954
    );
  UUT_delay_count_share0000_12_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      O => UUT_delay_count_share0000_12_LOGIC_ZERO_4001
    );
  UUT_delay_count_share0000_12_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_XORF_4021,
      O => UUT_delay_count_share0000(12)
    );
  UUT_delay_count_share0000_12_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      I0 => UUT_delay_count_share0000_12_CYINIT_4020,
      I1 => UUT_delay_count_share0000_12_F,
      O => UUT_delay_count_share0000_12_XORF_4021
    );
  UUT_delay_count_share0000_12_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_12_LOGIC_ZERO_4001,
      IB => UUT_delay_count_share0000_12_CYINIT_4020,
      SEL => UUT_delay_count_share0000_12_CYSELF_4007,
      O => UUT_Madd_delay_count_share0000_cy_12_Q
    );
  UUT_delay_count_share0000_12_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_12_LOGIC_ZERO_4001,
      IB => UUT_delay_count_share0000_12_LOGIC_ZERO_4001,
      SEL => UUT_delay_count_share0000_12_CYSELF_4007,
      O => UUT_delay_count_share0000_12_CYMUXF2_4002
    );
  UUT_delay_count_share0000_12_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_11_Q,
      O => UUT_delay_count_share0000_12_CYINIT_4020
    );
  UUT_delay_count_share0000_12_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_F,
      O => UUT_delay_count_share0000_12_CYSELF_4007
    );
  UUT_delay_count_share0000_12_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_XORG_4009,
      O => UUT_delay_count_share0000(13)
    );
  UUT_delay_count_share0000_12_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_12_Q,
      I1 => UUT_delay_count_share0000_12_G,
      O => UUT_delay_count_share0000_12_XORG_4009
    );
  UUT_delay_count_share0000_12_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X33Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_delay_count_share0000_cy_11_Q,
      O => UUT_delay_count_share0000_12_FASTCARRY_4004
    );
  UUT_delay_count_share0000_12_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      I0 => UUT_delay_count_share0000_12_CYSELG_3992,
      I1 => UUT_delay_count_share0000_12_CYSELF_4007,
      O => UUT_delay_count_share0000_12_CYAND_4005
    );
  UUT_delay_count_share0000_12_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_12_CYMUXG2_4003,
      IB => UUT_delay_count_share0000_12_FASTCARRY_4004,
      SEL => UUT_delay_count_share0000_12_CYAND_4005,
      O => UUT_delay_count_share0000_12_CYMUXFAST_4006
    );
  UUT_delay_count_share0000_12_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X33Y21"
    )
    port map (
      IA => UUT_delay_count_share0000_12_LOGIC_ZERO_4001,
      IB => UUT_delay_count_share0000_12_CYMUXF2_4002,
      SEL => UUT_delay_count_share0000_12_CYSELG_3992,
      O => UUT_delay_count_share0000_12_CYMUXG2_4003
    );
  UUT_delay_count_share0000_12_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X33Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_G,
      O => UUT_delay_count_share0000_12_CYSELG_3992
    );
  UUT_delay_count_share0000_14_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X33Y22"
    )
    port map (
      O => UUT_delay_count_share0000_14_LOGIC_ZERO_4051
    );
  UUT_delay_count_share0000_14_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_14_XORF_4052,
      O => UUT_delay_count_share0000(14)
    );
  UUT_delay_count_share0000_14_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X33Y22"
    )
    port map (
      I0 => UUT_delay_count_share0000_14_CYINIT_4050,
      I1 => UUT_delay_count_share0000_14_F,
      O => UUT_delay_count_share0000_14_XORF_4052
    );
  UUT_delay_count_share0000_14_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X33Y22"
    )
    port map (
      IA => UUT_delay_count_share0000_14_LOGIC_ZERO_4051,
      IB => UUT_delay_count_share0000_14_CYINIT_4050,
      SEL => UUT_delay_count_share0000_14_CYSELF_4041,
      O => UUT_Madd_delay_count_share0000_cy_14_Q
    );
  UUT_delay_count_share0000_14_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_12_CYMUXFAST_4006,
      O => UUT_delay_count_share0000_14_CYINIT_4050
    );
  UUT_delay_count_share0000_14_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_14_F,
      O => UUT_delay_count_share0000_14_CYSELF_4041
    );
  UUT_delay_count_share0000_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X33Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_share0000_14_XORG_4038,
      O => UUT_delay_count_share0000(15)
    );
  UUT_delay_count_share0000_14_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X33Y22"
    )
    port map (
      I0 => UUT_Madd_delay_count_share0000_cy_14_Q,
      I1 => UUT_delay_count_15_rt_4035,
      O => UUT_delay_count_share0000_14_XORG_4038
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X25Y53"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE_4068
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y53"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO_4083
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ZERO_4083,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT_4082,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF_4073,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYINIT_4082
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(0),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELF_4073
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X25Y53"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_1_LOGIC_ONE_4068,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_0_Q,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG_4060,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG_4070
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(1),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYSELG_4060
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X25Y54"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE_4098
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y54"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4114
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y54"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4114,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ZERO_4114,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4104,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2_4099
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(2),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4104
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X25Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_1_CYMUXG_4070,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY_4101
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X25Y54"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4091,
      I1 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELF_4104,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND_4102
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X25Y54"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2_4100,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_FASTCARRY_4101,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYAND_4102,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST_4103
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X25Y54"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0000_cy_3_LOGIC_ONE_4098,
      IB => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXF2_4099,
      SEL => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4091,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXG2_4100
    );
  UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X25Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(3),
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYSELG_4091
    );
  N45_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X25Y55"
    )
    port map (
      O => N45_LOGIC_ZERO_4141
    );
  N45_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X25Y55"
    )
    port map (
      IA => N45_LOGIC_ZERO_4141,
      IB => N45_CYINIT_4140,
      SEL => N45_CYSELF_4134,
      O => UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q
    );
  N45_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X25Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_cy_3_CYMUXFAST_4103,
      O => N45_CYINIT_4140
    );
  N45_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X25Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0000_lut(4),
      O => N45_CYSELF_4134
    );
  N45_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => N45,
      O => N45_0
    );
  CLK_clk_div_0_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X29Y35"
    )
    port map (
      O => CLK_clk_div_0_LOGIC_ZERO_4162
    );
  CLK_clk_div_0_LOGIC_ONE : X_ONE
    generic map(
      LOC => "SLICE_X29Y35"
    )
    port map (
      O => CLK_clk_div_0_LOGIC_ONE_4184
    );
  CLK_clk_div_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_XORF_4185,
      O => CLK_clk_div_0_DXMUX_4187
    );
  CLK_clk_div_0_XORF : X_XOR2
    generic map(
      LOC => "SLICE_X29Y35"
    )
    port map (
      I0 => CLK_clk_div_0_CYINIT_4183,
      I1 => CLK_Mcount_clk_div_lut(0),
      O => CLK_clk_div_0_XORF_4185
    );
  CLK_clk_div_0_CYMUXF : X_MUX2
    generic map(
      LOC => "SLICE_X29Y35"
    )
    port map (
      IA => CLK_clk_div_0_LOGIC_ONE_4184,
      IB => CLK_clk_div_0_CYINIT_4183,
      SEL => CLK_clk_div_0_CYSELF_4174,
      O => CLK_Mcount_clk_div_cy_0_Q
    );
  CLK_clk_div_0_CYINIT : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC0,
      O => CLK_clk_div_0_CYINIT_4183
    );
  CLK_clk_div_0_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_Mcount_clk_div_lut(0),
      O => CLK_clk_div_0_CYSELF_4174
    );
  CLK_clk_div_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_XORG_4165,
      O => CLK_clk_div_0_DYMUX_4167
    );
  CLK_clk_div_0_XORG : X_XOR2
    generic map(
      LOC => "SLICE_X29Y35"
    )
    port map (
      I0 => CLK_Mcount_clk_div_cy_0_Q,
      I1 => CLK_clk_div_0_G,
      O => CLK_clk_div_0_XORG_4165
    );
  CLK_clk_div_0_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_CYMUXG_4164,
      O => CLK_Mcount_clk_div_cy_1_Q
    );
  CLK_clk_div_0_CYMUXG : X_MUX2
    generic map(
      LOC => "SLICE_X29Y35"
    )
    port map (
      IA => CLK_clk_div_0_LOGIC_ZERO_4162,
      IB => CLK_Mcount_clk_div_cy_0_Q,
      SEL => CLK_clk_div_0_CYSELG_4153,
      O => CLK_clk_div_0_CYMUXG_4164
    );
  CLK_clk_div_0_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_clk_div_0_G,
      O => CLK_clk_div_0_CYSELG_4153
    );
  CLK_clk_div_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_clk_div_0_SRINV_4151
    );
  CLK_clk_div_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X29Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_clk_div_0_CLKINV_4150
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "SLICE_X31Y19"
    )
    port map (
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4541
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y19"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4541,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4541,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4547,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2_4542
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF : X_BUF
    generic map(
      LOC => "SLICE_X31Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(4),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4547
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_COUTUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST_4546,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY : X_BUF
    generic map(
      LOC => "SLICE_X31Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_cy_3_CYMUXFAST_4512,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY_4544
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND : X_AND2
    generic map(
      LOC => "SLICE_X31Y19"
    )
    port map (
      I0 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4534,
      I1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELF_4547,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND_4545
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST : X_MUX2
    generic map(
      LOC => "SLICE_X31Y19"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2_4543,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_FASTCARRY_4544,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYAND_4545,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXFAST_4546
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2 : X_MUX2
    generic map(
      LOC => "SLICE_X31Y19"
    )
    port map (
      IA => UUT_Mcompar_nstate_cmp_gt0002_cy_5_LOGIC_ZERO_4541,
      IB => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXF2_4542,
      SEL => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4534,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYMUXG2_4543
    );
  UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG : X_BUF
    generic map(
      LOC => "SLICE_X31Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Mcompar_nstate_cmp_gt0002_lut(5),
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_5_CYSELG_4534
    );
  I2C_Data_PULLUP : X_PU
    generic map(
      LOC => "PAD19"
    )
    port map (
      O => I2C_Data
    );
  IOBUF_inst_OBUFT : X_OBUFT
    generic map(
      LOC => "PAD19"
    )
    port map (
      I => I2C_Data_O,
      CTL => I2C_Data_T,
      O => I2C_Data
    );
  IOBUF_inst_IBUF : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => I2C_Data,
      O => I2C_Data_INBUF
    );
  I2C_Data_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => I2C_Data_INBUF,
      O => out_i2c
    );
  SW_0_IBUF : X_BUF
    generic map(
      LOC => "PAD124",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(0),
      O => SW_0_INBUF
    );
  SW_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD124",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_0_INBUF,
      O => SW_0_IBUF_2433
    );
  SW_1_IBUF : X_BUF
    generic map(
      LOC => "PAD117",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(1),
      O => SW_1_INBUF
    );
  SW_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD117",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_1_INBUF,
      O => SW_1_IBUF_2434
    );
  SW_2_IBUF : X_BUF
    generic map(
      LOC => "PAD116",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(2),
      O => SW_2_INBUF
    );
  SW_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD116",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_2_INBUF,
      O => SW_2_IBUF_2435
    );
  SW_3_IBUF : X_BUF
    generic map(
      LOC => "IPAD21",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW(3),
      O => SW_3_INBUF
    );
  FPGA_Clk_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "IPAD108",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk,
      O => FPGA_Clk_INBUF
    );
  I2C_Clk_PULLUP : X_PU
    generic map(
      LOC => "PAD18"
    )
    port map (
      O => I2C_Clk
    );
  I2C_Clk_OBUF : X_OBUF
    generic map(
      LOC => "PAD18"
    )
    port map (
      I => I2C_Clk_O,
      O => I2C_Clk
    );
  FPGA_Clk_BUFGP_BUFG : X_BUFGMUX
    generic map(
      LOC => "BUFGMUX_X2Y1"
    )
    port map (
      I0 => FPGA_Clk_BUFGP_BUFG_I0_INV,
      I1 => GND,
      S => FPGA_Clk_BUFGP_BUFG_S_INVNOT,
      O => FPGA_Clk_BUFGP
    );
  FPGA_Clk_BUFGP_BUFG_SINV : X_INV
    generic map(
      LOC => "BUFGMUX_X2Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => FPGA_Clk_BUFGP_BUFG_S_INVNOT
    );
  FPGA_Clk_BUFGP_BUFG_I0_USED : X_BUF
    generic map(
      LOC => "BUFGMUX_X2Y1",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_INBUF,
      O => FPGA_Clk_BUFGP_BUFG_I0_INV
    );
  UUT_Dir_mux000025_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000025_F5MUX_4641,
      O => UUT_Dir_mux000025
    );
  UUT_Dir_mux000025_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X22Y49"
    )
    port map (
      IA => N146,
      IB => N147,
      SEL => UUT_Dir_mux000025_BXINV_4634,
      O => UUT_Dir_mux000025_F5MUX_4641
    );
  UUT_Dir_mux000025_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_2439,
      O => UUT_Dir_mux000025_BXINV_4634
    );
  UUT_Dir_mux0000164_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000164_F5MUX_4666,
      O => UUT_Dir_mux0000164
    );
  UUT_Dir_mux0000164_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y50"
    )
    port map (
      IA => N136,
      IB => N137,
      SEL => UUT_Dir_mux0000164_BXINV_4659,
      O => UUT_Dir_mux0000164_F5MUX_4666
    );
  UUT_Dir_mux0000164_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count(0),
      O => UUT_Dir_mux0000164_BXINV_4659
    );
  UUT_ack_count_mux0000_0_10_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X16Y52"
    )
    port map (
      IA => N148,
      IB => N149,
      SEL => UUT_ack_count_mux0000_0_10_BXINV_4684,
      O => UUT_ack_count_mux0000_0_10_F5MUX_4691
    );
  UUT_ack_count_mux0000_0_10_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count(0),
      O => UUT_ack_count_mux0000_0_10_BXINV_4684
    );
  N53_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => N53_F5MUX_4716,
      O => N53
    );
  N53_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X24Y39"
    )
    port map (
      IA => N81,
      IB => N82,
      SEL => N53_BXINV_4709,
      O => N53_F5MUX_4716
    );
  N53_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0001_0,
      O => N53_BXINV_4709
    );
  N54_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N54_F5MUX_4741,
      O => N54
    );
  N54_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X24Y38"
    )
    port map (
      IA => N83,
      IB => N84,
      SEL => N54_BXINV_4732,
      O => N54_F5MUX_4741
    );
  N54_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0001_0,
      O => N54_BXINV_4732
    );
  UUT_nstate_FFd3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_F5MUX_4770,
      O => UUT_nstate_FFd3_DXMUX_4772
    );
  UUT_nstate_FFd3_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y41"
    )
    port map (
      IA => UUT_nstate_FFd3_G,
      IB => UUT_nstate_FFd3_In311,
      SEL => UUT_nstate_FFd3_BXINV_4763,
      O => UUT_nstate_FFd3_F5MUX_4770
    );
  UUT_nstate_FFd3_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_2442,
      O => UUT_nstate_FFd3_BXINV_4763
    );
  UUT_nstate_FFd3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_In14_8785,
      O => UUT_nstate_FFd3_SRINV_4752
    );
  UUT_nstate_FFd3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd3_CLKINV_4751
    );
  UUT_shiftReg_mux0000_1_8_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X24Y35"
    )
    port map (
      IA => N144,
      IB => N145,
      SEL => UUT_shiftReg_mux0000_1_8_BXINV_4793,
      O => UUT_shiftReg_mux0000_1_8_F5MUX_4800
    );
  UUT_shiftReg_mux0000_1_8_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_2442,
      O => UUT_shiftReg_mux0000_1_8_BXINV_4793
    );
  UUT_shiftReg_mux0000_4_8_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X24Y30"
    )
    port map (
      IA => N142,
      IB => N143,
      SEL => UUT_shiftReg_mux0000_4_8_BXINV_4818,
      O => UUT_shiftReg_mux0000_4_8_F5MUX_4825
    );
  UUT_shiftReg_mux0000_4_8_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_2442,
      O => UUT_shiftReg_mux0000_4_8_BXINV_4818
    );
  UUT_nstate_FFd2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_F5MUX_4854,
      O => UUT_nstate_FFd2_DXMUX_4856
    );
  UUT_nstate_FFd2_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X25Y39"
    )
    port map (
      IA => N152,
      IB => N153,
      SEL => UUT_nstate_FFd2_BXINV_4847,
      O => UUT_nstate_FFd2_F5MUX_4854
    );
  UUT_nstate_FFd2_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_2442,
      O => UUT_nstate_FFd2_BXINV_4847
    );
  UUT_nstate_FFd2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_In27_8821,
      O => UUT_nstate_FFd2_SRINV_4840
    );
  UUT_nstate_FFd2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd2_CLKINV_4839
    );
  UUT_nstate_FFd2_In771_F : X_LUT4
    generic map(
      INIT => X"AE26",
      LOC => "SLICE_X25Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => N152
    );
  UUT_counter_mux0000_0_F : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X12Y38"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_counter(3),
      ADR2 => UUT_Madd_counter_addsub0000_cy_2_0,
      ADR3 => UUT_nstate_cmp_eq0012_0,
      O => N138
    );
  UUT_counter_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X12Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_4_F5MUX_4886,
      O => UUT_counter_4_DXMUX_4888
    );
  UUT_counter_4_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X12Y38"
    )
    port map (
      IA => N138,
      IB => N139,
      SEL => UUT_counter_4_BXINV_4879,
      O => UUT_counter_4_F5MUX_4886
    );
  UUT_counter_4_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X12Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter(4),
      O => UUT_counter_4_BXINV_4879
    );
  UUT_counter_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X12Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_4_CLKINV_4872
    );
  UUT_counter_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X12Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_3_F5MUX_4917,
      O => UUT_counter_3_DXMUX_4919
    );
  UUT_counter_3_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X12Y39"
    )
    port map (
      IA => N132,
      IB => N133,
      SEL => UUT_counter_3_BXINV_4910,
      O => UUT_counter_3_F5MUX_4917
    );
  UUT_counter_3_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X12Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_counter_addsub0000_cy_2_0,
      O => UUT_counter_3_BXINV_4910
    );
  UUT_counter_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X12Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_3_CLKINV_4902
    );
  UUT_counter_mux0000_1_F : X_LUT4
    generic map(
      INIT => X"CC88",
      LOC => "SLICE_X12Y39"
    )
    port map (
      ADR0 => UUT_N62,
      ADR1 => UUT_counter(3),
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd1_2439,
      O => N132
    );
  UUT_counter_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X13Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_2_F5MUX_4948,
      O => UUT_counter_2_DXMUX_4950
    );
  UUT_counter_2_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X13Y39"
    )
    port map (
      IA => N140,
      IB => N141,
      SEL => UUT_counter_2_BXINV_4941,
      O => UUT_counter_2_F5MUX_4948
    );
  UUT_counter_2_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X13Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter(2),
      O => UUT_counter_2_BXINV_4941
    );
  UUT_counter_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X13Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_2_CLKINV_4934
    );
  UUT_counter_mux0000_2_F : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X13Y39"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0012_0,
      ADR1 => UUT_counter(1),
      ADR2 => UUT_counter(0),
      ADR3 => UUT_ClkRisingEdge_2447,
      O => N140
    );
  UUT_counter_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X15Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_1_F5MUX_4979,
      O => UUT_counter_1_DXMUX_4981
    );
  UUT_counter_1_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X15Y39"
    )
    port map (
      IA => N134,
      IB => N135,
      SEL => UUT_counter_1_BXINV_4971,
      O => UUT_counter_1_F5MUX_4979
    );
  UUT_counter_1_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter(1),
      O => UUT_counter_1_BXINV_4971
    );
  UUT_counter_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X15Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_1_CLKINV_4964
    );
  UUT_counter_mux0000_3_F : X_LUT4
    generic map(
      INIT => X"4000",
      LOC => "SLICE_X15Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => UUT_counter(0),
      ADR3 => UUT_ClkRisingEdge_2447,
      O => N134
    );
  UUT_nstate_FFd4_In14_F5MUX : X_MUX2
    generic map(
      LOC => "SLICE_X23Y44"
    )
    port map (
      IA => N150,
      IB => N151,
      SEL => UUT_nstate_FFd4_In14_BXINV_5001,
      O => UUT_nstate_FFd4_In14_F5MUX_5008
    );
  UUT_nstate_FFd4_In14_BXINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y44",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_2441,
      O => UUT_nstate_FFd4_In14_BXINV_5001
    );
  N64_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => N64,
      O => N64_0
    );
  N64_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0014_pack_1,
      O => UUT_nstate_cmp_eq0014
    );
  UUT_nstate_Out81 : X_LUT4
    generic map(
      INIT => X"0030",
      LOC => "SLICE_X23Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_nstate_cmp_eq0014_pack_1
    );
  UUT_Dir_mux000083_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000083_5055,
      O => UUT_Dir_mux000083_0
    );
  UUT_Dir_mux000083_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_or0001_pack_1,
      O => UUT_delay_count_or0001
    );
  UUT_delay_count_or00011 : X_LUT4
    generic map(
      INIT => X"BAA0",
      LOC => "SLICE_X24Y24"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd2_2441,
      O => UUT_delay_count_or0001_pack_1
    );
  UUT_pstate_4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X26Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000(5),
      O => UUT_pstate_4_DXMUX_5084
    );
  UUT_pstate_4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_7_11104_SW2_O_pack_1,
      O => UUT_pstate_mux0000_7_11104_SW2_O
    );
  UUT_pstate_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X26Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_pstate_4_CLKINV_5069
    );
  UUT_pstate_mux0000_7_11104_SW2 : X_LUT4
    generic map(
      INIT => X"ABFB",
      LOC => "SLICE_X26Y38"
    )
    port map (
      ADR0 => N40_0,
      ADR1 => N54,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR3 => N53,
      O => UUT_pstate_mux0000_7_11104_SW2_O_pack_1
    );
  UUT_pstate_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X25Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000(6),
      O => UUT_pstate_3_DXMUX_5114
    );
  UUT_pstate_3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_7_11104_SW1_O_pack_1,
      O => UUT_pstate_mux0000_7_11104_SW1_O
    );
  UUT_pstate_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X25Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_pstate_3_CLKINV_5099
    );
  UUT_pstate_mux0000_7_11104_SW1 : X_LUT4
    generic map(
      INIT => X"C480",
      LOC => "SLICE_X25Y38"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR1 => N37_0,
      ADR2 => N53,
      ADR3 => N54,
      O => UUT_pstate_mux0000_7_11104_SW1_O_pack_1
    );
  N111_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => N111,
      O => N111_0
    );
  N111_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N44_pack_1,
      O => UUT_N44
    );
  UUT_out_i2cclk_mux0000111 : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X16Y55"
    )
    port map (
      ADR0 => UUT_ack_count(7),
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(2),
      O => UUT_N44_pack_1
    );
  UUT_N32_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N32,
      O => UUT_N32_0
    );
  UUT_N32_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux00003_SW0_O_pack_1,
      O => UUT_out_i2cclk_mux00003_SW0_O
    );
  UUT_out_i2cclk_mux00003_SW0 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X16Y54"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_ack_count(11),
      ADR3 => UUT_ack_count(10),
      O => UUT_out_i2cclk_mux00003_SW0_O_pack_1
    );
  UUT_ack_count_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_cmp_eq0000_5187,
      O => UUT_ack_count_cmp_eq0000_0
    );
  UUT_ack_count_cmp_eq0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N100_pack_1,
      O => UUT_N100
    );
  UUT_ack_count_cmp_eq000011 : X_LUT4
    generic map(
      INIT => X"0003",
      LOC => "SLICE_X19Y52"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_ack_count(4),
      O => UUT_N100_pack_1
    );
  UUT_N2116_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N2116_5211,
      O => UUT_N2116_0
    );
  UUT_N2116_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux000078_pack_1,
      O => UUT_in_i2c_mux000078
    );
  UUT_ack_count_or000421 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X14Y50"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(4),
      ADR3 => UUT_ack_count(3),
      O => UUT_in_i2c_mux000078_pack_1
    );
  UUT_N2140_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N2140_5235,
      O => UUT_N2140_0
    );
  UUT_N2140_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_and0023_pack_1,
      O => UUT_ack_count_and0023
    );
  UUT_ack_count_and00231 : X_LUT4
    generic map(
      INIT => X"1111",
      LOC => "SLICE_X14Y53"
    )
    port map (
      ADR0 => UUT_N32_0,
      ADR1 => UUT_ack_count(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_and0023_pack_1
    );
  UUT_N2181_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N2181_5259,
      O => UUT_N2181_0
    );
  UUT_N2181_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N2181_SW0_O_pack_1,
      O => UUT_N2181_SW0_O
    );
  UUT_N2181_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X18Y56"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_ack_count(4),
      ADR3 => UUT_ack_count(1),
      O => UUT_N2181_SW0_O_pack_1
    );
  UUT_Dir_mux0000230_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000230_5283,
      O => UUT_Dir_mux0000230_0
    );
  UUT_Dir_mux0000230_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000205_O_pack_1,
      O => UUT_Dir_mux0000205_O
    );
  UUT_Dir_mux0000205 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X23Y50"
    )
    port map (
      ADR0 => UUT_N44,
      ADR1 => UUT_Dir_mux0000203_0,
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_Dir_mux0000205_O_pack_1
    );
  UUT_Dir_mux0000178_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000178_5307,
      O => UUT_Dir_mux0000178_0
    );
  UUT_Dir_mux0000178_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N1111_pack_1,
      O => UUT_N1111
    );
  UUT_Dir_mux0000231 : X_LUT4
    generic map(
      INIT => X"0C0C",
      LOC => "SLICE_X22Y50"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_ack_count(5),
      ADR3 => VCC,
      O => UUT_N1111_pack_1
    );
  UUT_shiftReg_and0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_and0000,
      O => UUT_shiftReg_and0000_0
    );
  UUT_shiftReg_and0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq00031_SW1_O_pack_1,
      O => UUT_shiftReg_cmp_eq00031_SW1_O
    );
  UUT_shiftReg_cmp_eq00031_SW1 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X30Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(8),
      ADR2 => UUT_delay_count(5),
      ADR3 => UUT_delay_count(11),
      O => UUT_shiftReg_cmp_eq00031_SW1_O_pack_1
    );
  UUT_ack_count_mux0000_0_45_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_45_5355,
      O => UUT_ack_count_mux0000_0_45_0
    );
  UUT_ack_count_mux0000_0_45_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_45_SW0_O_pack_1,
      O => UUT_ack_count_mux0000_0_45_SW0_O
    );
  UUT_shiftReg_mux0000_0_210_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_210_5919,
      O => UUT_shiftReg_mux0000_0_210_0
    );
  UUT_shiftReg_mux0000_0_210_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_28_pack_1,
      O => UUT_shiftReg_mux0000_0_28_2476
    );
  UUT_shiftReg_mux0000_0_28 : X_LUT4
    generic map(
      INIT => X"ECFC",
      LOC => "SLICE_X22Y32"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_cmp_eq0007,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_ClkRisingEdge_2447,
      O => UUT_shiftReg_mux0000_0_28_pack_1
    );
  UUT_N26_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N26,
      O => UUT_N26_0
    );
  UUT_N26_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y22",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N42_pack_1,
      O => UUT_N42
    );
  UUT_shiftReg_cmp_eq00032 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X25Y22"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => N31_0,
      ADR2 => UUT_delay_count(7),
      ADR3 => UUT_delay_count(6),
      O => UUT_N42_pack_1
    );
  UUT_N29_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N29,
      O => UUT_N29_0
    );
  UUT_N29_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000122_pack_1,
      O => UUT_Dir_mux0000122_2573
    );
  UUT_Dir_mux0000122 : X_LUT4
    generic map(
      INIT => X"0505",
      LOC => "SLICE_X24Y27"
    )
    port map (
      ADR0 => UUT_delay_count(5),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(2),
      ADR3 => VCC,
      O => UUT_Dir_mux0000122_pack_1
    );
  UUT_shiftReg_mux0000_0_232_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_232_5991,
      O => UUT_shiftReg_mux0000_0_232_0
    );
  UUT_shiftReg_mux0000_0_232_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_218_O_pack_1,
      O => UUT_shiftReg_mux0000_0_218_O
    );
  UUT_shiftReg_mux0000_0_218 : X_LUT4
    generic map(
      INIT => X"0010",
      LOC => "SLICE_X24Y26"
    )
    port map (
      ADR0 => UUT_delay_count(0),
      ADR1 => UUT_delay_count(1),
      ADR2 => UUT_N42,
      ADR3 => UUT_shiftReg_cmp_eq0001,
      O => UUT_shiftReg_mux0000_0_218_O_pack_1
    );
  UUT_shiftReg_mux0000_0_316_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_316_6015,
      O => UUT_shiftReg_mux0000_0_316_0
    );
  UUT_shiftReg_mux0000_0_316_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or0000_pack_1,
      O => UUT_shiftReg_or0000
    );
  UUT_shiftReg_or000047 : X_LUT4
    generic map(
      INIT => X"FEFC",
      LOC => "SLICE_X26Y25"
    )
    port map (
      ADR0 => UUT_shiftReg_or000017_0,
      ADR1 => UUT_N79_0,
      ADR2 => UUT_shiftReg_or000032_0,
      ADR3 => UUT_delay_count(10),
      O => UUT_shiftReg_or0000_pack_1
    );
  UUT_N25_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N25,
      O => UUT_N25_0
    );
  UUT_N25_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_39_pack_1,
      O => UUT_shiftReg_mux0000_0_39_2581
    );
  UUT_shiftReg_mux0000_0_39 : X_LUT4
    generic map(
      INIT => X"A0EC",
      LOC => "SLICE_X24Y29"
    )
    port map (
      ADR0 => UUT_N29_0,
      ADR1 => UUT_nstate_cmp_eq0011_0,
      ADR2 => UUT_shiftReg_mux0000_0_30_0,
      ADR3 => UUT_N26_0,
      O => UUT_shiftReg_mux0000_0_39_pack_1
    );
  UUT_N15_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N15,
      O => UUT_N15_0
    );
  UUT_N15_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_215_pack_1,
      O => UUT_shiftReg_mux0000_0_215_2583
    );
  UUT_shiftReg_mux0000_0_215 : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X22Y28"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_cmp_eq0011_0,
      ADR2 => UUT_N26_0,
      ADR3 => VCC,
      O => UUT_shiftReg_mux0000_0_215_pack_1
    );
  UUT_out_i2cclk_mux0000227_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000227_6087,
      O => UUT_out_i2cclk_mux0000227_0
    );
  UUT_out_i2cclk_mux0000227_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000218_O_pack_1,
      O => UUT_out_i2cclk_mux0000218_O
    );
  UUT_out_i2cclk_mux0000218 : X_LUT4
    generic map(
      INIT => X"0FFF",
      LOC => "SLICE_X18Y57"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(6),
      O => UUT_out_i2cclk_mux0000218_O_pack_1
    );
  N58_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => N58,
      O => N58_0
    );
  N58_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_7_SW1_O_pack_1,
      O => UUT_pstate_mux0000_7_SW1_O
    );
  UUT_pstate_mux0000_7_SW1 : X_LUT4
    generic map(
      INIT => X"E200",
      LOC => "SLICE_X26Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR3 => UUT_nstate_FFd3_2440,
      O => UUT_pstate_mux0000_7_SW1_O_pack_1
    );
  UUT_out_i2cclk_mux0000258_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000258_6135,
      O => UUT_out_i2cclk_mux0000258_0
    );
  UUT_out_i2cclk_mux0000258_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y56",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000258_SW0_O_pack_1,
      O => UUT_out_i2cclk_mux0000258_SW0_O
    );
  UUT_out_i2cclk_mux0000258_SW0 : X_LUT4
    generic map(
      INIT => X"0101",
      LOC => "SLICE_X19Y56"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(2),
      ADR3 => VCC,
      O => UUT_out_i2cclk_mux0000258_SW0_O_pack_1
    );
  UUT_shiftReg_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_5_11,
      O => UUT_shiftReg_5_DXMUX_6166
    );
  UUT_shiftReg_5_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_257_SW3_O_pack_1,
      O => UUT_shiftReg_mux0000_0_257_SW3_O
    );
  UUT_shiftReg_5_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_5_0_6306,
      O => UUT_shiftReg_5_SRINV_6151
    );
  UUT_shiftReg_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_5_CLKINV_6150
    );
  N19_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => N19,
      O => N19_0
    );
  N19_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_or0000_pack_1,
      O => UUT_delay_count_or0000
    );
  UUT_delay_count_or00001 : X_LUT4
    generic map(
      INIT => X"ABAF",
      LOC => "SLICE_X21Y8"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_delay_count_or0000_pack_1
    );
  UUT_nstate_cmp_eq0001_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0001_6216,
      O => UUT_nstate_cmp_eq0001_0
    );
  UUT_nstate_cmp_eq0001_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_cmp_eq0000_pack_1,
      O => UUT_in_i2c_cmp_eq0000
    );
  UUT_nstate_cmp_eq000111 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X23Y52"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_N101,
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_N1111,
      O => UUT_in_i2c_cmp_eq0000_pack_1
    );
  UUT_shiftReg_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_7_10,
      O => UUT_shiftReg_7_DXMUX_6247
    );
  UUT_shiftReg_7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_257_SW1_O_pack_1,
      O => UUT_shiftReg_mux0000_0_257_SW1_O
    );
  UUT_shiftReg_7_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_7_5_8560,
      O => UUT_shiftReg_7_SRINV_6231
    );
  UUT_shiftReg_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_7_CLKINV_6230
    );
  UUT_shiftReg_2_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_2_1_6277,
      O => UUT_shiftReg_2_DXMUX_6280
    );
  UUT_shiftReg_2_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_2_SW0_O_pack_1,
      O => UUT_shiftReg_mux0000_2_SW0_O
    );
  UUT_shiftReg_2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0006_0,
      O => UUT_shiftReg_2_SRINV_6264
    );
  UUT_shiftReg_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_2_CLKINV_6263
    );
  UUT_shiftReg_mux0000_5_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y28",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_328_SW0_O_pack_1,
      O => UUT_shiftReg_mux0000_0_328_SW0_O
    );
  UUT_shiftReg_mux0000_0_328_SW0 : X_LUT4
    generic map(
      INIT => X"EECE",
      LOC => "SLICE_X24Y28"
    )
    port map (
      ADR0 => UUT_N0,
      ADR1 => UUT_nstate_cmp_eq0011_0,
      ADR2 => UUT_shiftReg_and0000_0,
      ADR3 => UUT_shiftReg_or0000,
      O => UUT_shiftReg_mux0000_0_328_SW0_O_pack_1
    );
  UUT_N33_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N33,
      O => UUT_N33_0
    );
  UUT_N33_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X30Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => N25_pack_1,
      O => N25
    );
  UUT_shiftReg_cmp_eq00031_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X30Y20"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => UUT_delay_count(12),
      ADR2 => UUT_delay_count(14),
      ADR3 => UUT_delay_count(13),
      O => N25_pack_1
    );
  UUT_nstate_FFd1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_In42,
      O => UUT_nstate_FFd1_DXMUX_6361
    );
  UUT_nstate_FFd1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_In33_O_pack_1,
      O => UUT_nstate_FFd1_In33_O
    );
  UUT_nstate_FFd1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd1_In0_8480,
      O => UUT_nstate_FFd1_SRINV_6345
    );
  UUT_nstate_FFd1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd1_CLKINV_6344
    );
  N93_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => N93,
      O => N93_0
    );
  N93_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N38_pack_1,
      O => UUT_N38
    );
  UUT_ack_count_mux0000_0_38 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X18Y52"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(4),
      O => UUT_N38_pack_1
    );
  UUT_out_i2cclk_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000131,
      O => UUT_out_i2cclk_DXMUX_6418
    );
  UUT_out_i2cclk_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000097_O_pack_1,
      O => UUT_out_i2cclk_mux000097_O
    );
  UUT_out_i2cclk_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000030_5451,
      O => UUT_out_i2cclk_SRINV_6402
    );
  UUT_out_i2cclk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_out_i2cclk_CLKINV_6401
    );
  UUT_N17_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N17,
      O => UUT_N17_0
    );
  UUT_N17_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N107_pack_1,
      O => UUT_N107
    );
  UUT_delay_count_mux0000_0_31 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "SLICE_X25Y20"
    )
    port map (
      ADR0 => UUT_delay_count_and0000_0,
      ADR1 => UUT_delay_count_or0001,
      ADR2 => UUT_N42,
      ADR3 => UUT_delay_count(2),
      O => UUT_N107_pack_1
    );
  UUT_ack_count_mux0000_0_45_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X14Y52"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_ack_count_mux0000_0_45_SW0_O_pack_1
    );
  UUT_pstate_mux0000_7_1115_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_7_1115_5379,
      O => UUT_pstate_mux0000_7_1115_0
    );
  UUT_pstate_mux0000_7_1115_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0007_pack_1,
      O => UUT_nstate_cmp_eq0007
    );
  UUT_nstate_Out11 : X_LUT4
    generic map(
      INIT => X"0500",
      LOC => "SLICE_X23Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_nstate_cmp_eq0007_pack_1
    );
  UUT_pstate_mux0000_7_1137_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_7_1137_5403,
      O => UUT_pstate_mux0000_7_1137_0
    );
  UUT_pstate_mux0000_7_1137_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In62_pack_1,
      O => UUT_nstate_FFd4_In62_2521
    );
  UUT_nstate_FFd4_In62 : X_LUT4
    generic map(
      INIT => X"D0F0",
      LOC => "SLICE_X22Y41"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_N32_0,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_N41_0,
      O => UUT_nstate_FFd4_In62_pack_1
    );
  UUT_N79_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N79,
      O => UUT_N79_0
    );
  UUT_N79_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or00002_SW0_O_pack_1,
      O => UUT_shiftReg_or00002_SW0_O
    );
  UUT_shiftReg_or00002_SW0 : X_LUT4
    generic map(
      INIT => X"0303",
      LOC => "SLICE_X26Y23"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(4),
      ADR2 => UUT_delay_count(6),
      ADR3 => VCC,
      O => UUT_shiftReg_or00002_SW0_O_pack_1
    );
  UUT_out_i2cclk_mux000030_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000018_O_pack_1,
      O => UUT_out_i2cclk_mux000018_O
    );
  UUT_out_i2cclk_mux000018 : X_LUT4
    generic map(
      INIT => X"F111",
      LOC => "SLICE_X20Y55"
    )
    port map (
      ADR0 => UUT_N37,
      ADR1 => N111_0,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1,
      ADR3 => UUT_N22,
      O => UUT_out_i2cclk_mux000018_O_pack_1
    );
  UUT_ack_count_6_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(6),
      O => UUT_ack_count_6_DXMUX_5480
    );
  UUT_ack_count_6_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N20_pack_1,
      O => UUT_N20
    );
  UUT_ack_count_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_6_CLKINV_5465
    );
  UUT_ack_count_mux0000_3_11 : X_LUT4
    generic map(
      INIT => X"40FF",
      LOC => "SLICE_X17Y55"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_nstate_cmp_eq0007,
      ADR2 => UUT_ack_count_cmp_eq0000_0,
      ADR3 => UUT_nstate_FFd3_In1_0,
      O => UUT_N20_pack_1
    );
  UUT_out_i2cclk_mux000080_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000080_5505,
      O => UUT_out_i2cclk_mux000080_0
    );
  UUT_out_i2cclk_mux000080_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000064_O_pack_1,
      O => UUT_out_i2cclk_mux000064_O
    );
  UUT_out_i2cclk_mux000064 : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X18Y54"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_ack_count(5),
      O => UUT_out_i2cclk_mux000064_O_pack_1
    );
  UUT_N21151_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N21151_5529,
      O => UUT_N21151_0
    );
  UUT_N21151_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N21130_O_pack_1,
      O => UUT_N21130_O
    );
  UUT_N21130 : X_LUT4
    generic map(
      INIT => X"575F",
      LOC => "SLICE_X19Y54"
    )
    port map (
      ADR0 => UUT_ack_count(7),
      ADR1 => N91_0,
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_ack_count(3),
      O => UUT_N21130_O_pack_1
    );
  UUT_N21_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N21,
      O => UUT_N21_0
    );
  UUT_N21_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N217_O_pack_1,
      O => UUT_N217_O
    );
  UUT_N217 : X_LUT4
    generic map(
      INIT => X"8F88",
      LOC => "SLICE_X18Y53"
    )
    port map (
      ADR0 => UUT_N37,
      ADR1 => UUT_counter_mux0000_4_7_0,
      ADR2 => UUT_ack_count_cmp_eq0000_0,
      ADR3 => UUT_nstate_cmp_eq0007,
      O => UUT_N217_O_pack_1
    );
  UUT_in_i2c_and0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_and0000,
      O => UUT_in_i2c_and0000_0
    );
  UUT_in_i2c_and0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N37_pack_1,
      O => UUT_N37
    );
  UUT_Dir_mux000031 : X_LUT4
    generic map(
      INIT => X"FFFA",
      LOC => "SLICE_X14Y55"
    )
    port map (
      ADR0 => UUT_ack_count(11),
      ADR1 => VCC,
      ADR2 => UUT_ack_count(10),
      ADR3 => UUT_ack_count(9),
      O => UUT_N37_pack_1
    );
  UUT_Dir_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000243,
      O => UUT_Dir_DXMUX_5608
    );
  UUT_Dir_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000092_O_pack_1,
      O => UUT_Dir_mux000092_O
    );
  UUT_Dir_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000128_8273,
      O => UUT_Dir_SRINV_5592
    );
  UUT_Dir_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_Dir_CLKINV_5591
    );
  N117_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N117,
      O => N117_0
    );
  N117_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0000_pack_1,
      O => UUT_nstate_cmp_eq0000_2545
    );
  UUT_nstate_cmp_eq0000 : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X16Y40"
    )
    port map (
      ADR0 => UUT_counter(0),
      ADR1 => UUT_counter(2),
      ADR2 => N21_0,
      ADR3 => UUT_counter(3),
      O => UUT_nstate_cmp_eq0000_pack_1
    );
  UUT_shiftReg_mux0000_0_30_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_30_5658,
      O => UUT_shiftReg_mux0000_0_30_0
    );
  UUT_shiftReg_mux0000_0_30_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y25",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N0_pack_1,
      O => UUT_N0
    );
  UUT_shiftReg_mux0000_0_11 : X_LUT4
    generic map(
      INIT => X"C8C8",
      LOC => "SLICE_X27Y25"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => VCC,
      O => UUT_N0_pack_1
    );
  UUT_writeCount_8_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(8),
      O => UUT_writeCount_8_DXMUX_5687
    );
  UUT_writeCount_8_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N31_pack_1,
      O => UUT_N31
    );
  UUT_writeCount_8_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y5",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_8_CLKINV_5671
    );
  UUT_writeCount_mux0000_10_21 : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X16Y5"
    )
    port map (
      ADR0 => UUT_delay_count_or0001,
      ADR1 => UUT_N26_0,
      ADR2 => UUT_ClkFallingEdge_2553,
      ADR3 => VCC,
      O => UUT_N31_pack_1
    );
  UUT_writeCount_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(9),
      O => UUT_writeCount_9_DXMUX_5717
    );
  UUT_writeCount_9_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N11_pack_1,
      O => UUT_N11
    );
  UUT_writeCount_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_9_CLKINV_5702
    );
  UUT_writeCount_mux0000_10_11 : X_LUT4
    generic map(
      INIT => X"F0F8",
      LOC => "SLICE_X16Y4"
    )
    port map (
      ADR0 => UUT_delay_count_or0001,
      ADR1 => UUT_N26_0,
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_ClkFallingEdge_2553,
      O => UUT_N11_pack_1
    );
  UUT_shiftReg_mux0000_3_14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N46_pack_1,
      O => UUT_N46
    );
  UUT_in_i2c_mux000121 : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X23Y34"
    )
    port map (
      ADR0 => UUT_shiftReg_and0000_0,
      ADR1 => UUT_shiftReg_cmp_eq0002_0,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_N46_pack_1
    );
  UUT_shiftReg_cmp_eq0002_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0002,
      O => UUT_shiftReg_cmp_eq0002_0
    );
  UUT_shiftReg_cmp_eq0002_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux00012_SW0_O_pack_1,
      O => UUT_Dir_mux00012_SW0_O
    );
  UUT_Dir_mux00012_SW0 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X25Y24"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_delay_count(4),
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_delay_count(0),
      O => UUT_Dir_mux00012_SW0_O_pack_1
    );
  UUT_ack_count_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_97,
      O => UUT_ack_count_0_DXMUX_5797
    );
  UUT_ack_count_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_68_O_pack_1,
      O => UUT_ack_count_mux0000_0_68_O
    );
  UUT_ack_count_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_0_10_F5MUX_4691,
      O => UUT_ack_count_0_SRINV_5781
    );
  UUT_ack_count_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_0_CLKINV_5780
    );
  UUT_ack_count_mux0000_0_68 : X_LUT4
    generic map(
      INIT => X"0D00",
      LOC => "SLICE_X16Y53"
    )
    port map (
      ADR0 => N89_0,
      ADR1 => UUT_ack_count_mux0000_0_45_0,
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_N38,
      O => UUT_ack_count_mux0000_0_68_O_pack_1
    );
  UUT_ack_count_mux0000_10_210_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_10_210_5823,
      O => UUT_ack_count_mux0000_10_210_0
    );
  UUT_ack_count_mux0000_10_210_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0015_pack_1,
      O => UUT_nstate_cmp_eq0015
    );
  UUT_nstate_Out91 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X17Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_nstate_cmp_eq0015_pack_1
    );
  UUT_N16_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N16,
      O => UUT_N16_0
    );
  UUT_N16_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000_10_20_O_pack_1,
      O => UUT_ack_count_mux0000_10_20_O
    );
  UUT_ack_count_mux0000_10_20 : X_LUT4
    generic map(
      INIT => X"1000",
      LOC => "SLICE_X17Y52"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_ack_count_cmp_eq0000_0,
      O => UUT_ack_count_mux0000_10_20_O_pack_1
    );
  UUT_counter_mux0000_4_20_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N40_pack_1,
      O => UUT_N40
    );
  UUT_counter_mux0000_4_110 : X_LUT4
    generic map(
      INIT => X"0A0A",
      LOC => "SLICE_X19Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => VCC,
      O => UUT_N40_pack_1
    );
  UUT_shiftReg_or000012 : X_LUT4
    generic map(
      INIT => X"5F5F",
      LOC => "SLICE_X26Y24"
    )
    port map (
      ADR0 => UUT_delay_count(0),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(6),
      ADR3 => VCC,
      O => UUT_shiftReg_or000012_O_pack_1
    );
  UUT_shiftReg_or000017_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or000017_5895,
      O => UUT_shiftReg_or000017_0
    );
  UUT_shiftReg_or000017_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X26Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or000012_O_pack_1,
      O => UUT_shiftReg_or000012_O
    );
  UUT_nstate_FFd4_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In85,
      O => UUT_nstate_FFd4_DXMUX_6475
    );
  UUT_nstate_FFd4_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In28_O_pack_1,
      O => UUT_nstate_FFd4_In28_O
    );
  UUT_nstate_FFd4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In14_F5MUX_5008,
      O => UUT_nstate_FFd4_SRINV_6460
    );
  UUT_nstate_FFd4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_nstate_FFd4_CLKINV_6459
    );
  UUT_in_i2c_mux000034_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux000034_6501,
      O => UUT_in_i2c_mux000034_0
    );
  UUT_in_i2c_mux000034_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux000032_O_pack_1,
      O => UUT_in_i2c_mux000032_O
    );
  UUT_in_i2c_mux000032 : X_LUT4
    generic map(
      INIT => X"4000",
      LOC => "SLICE_X20Y52"
    )
    port map (
      ADR0 => UUT_N37,
      ADR1 => UUT_N1111,
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_ack_count(0),
      O => UUT_in_i2c_mux000032_O_pack_1
    );
  UUT_delay_count_mux0000_0_125_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_125_6525,
      O => UUT_delay_count_mux0000_0_125_0
    );
  UUT_delay_count_mux0000_0_125_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X29Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_125_SW0_O_pack_1,
      O => UUT_delay_count_mux0000_0_125_SW0_O
    );
  UUT_delay_count_mux0000_0_125_SW0 : X_LUT4
    generic map(
      INIT => X"A0A0",
      LOC => "SLICE_X29Y21"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(4),
      ADR3 => VCC,
      O => UUT_delay_count_mux0000_0_125_SW0_O_pack_1
    );
  UUT_N41_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N41,
      O => UUT_N41_0
    );
  UUT_N41_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N101_pack_1,
      O => UUT_N101
    );
  UUT_Dir_mux000061 : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X20Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(4),
      ADR3 => UUT_ack_count(3),
      O => UUT_N101_pack_1
    );
  UUT_in_i2c_mux000063_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000211_O_pack_1,
      O => UUT_in_i2c_mux0000211_O
    );
  UUT_in_i2c_mux0000211 : X_LUT4
    generic map(
      INIT => X"0004",
      LOC => "SLICE_X19Y53"
    )
    port map (
      ADR0 => UUT_N32_0,
      ADR1 => UUT_nstate_cmp_eq0015,
      ADR2 => UUT_ack_count(0),
      ADR3 => N95_0,
      O => UUT_in_i2c_mux0000211_O_pack_1
    );
  UUT_in_i2c_mux0000144_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000144_6597,
      O => UUT_in_i2c_mux0000144_0
    );
  UUT_in_i2c_mux0000144_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000131_O_pack_1,
      O => UUT_in_i2c_mux0000131_O
    );
  UUT_in_i2c_mux0000131 : X_LUT4
    generic map(
      INIT => X"77FF",
      LOC => "SLICE_X20Y50"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_ack_count(3),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(7),
      O => UUT_in_i2c_mux0000131_O_pack_1
    );
  UUT_N3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N3,
      O => UUT_N3_0
    );
  UUT_N3_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_145_O_pack_1,
      O => UUT_delay_count_mux0000_0_145_O
    );
  UUT_delay_count_mux0000_0_145 : X_LUT4
    generic map(
      INIT => X"EEFF",
      LOC => "SLICE_X27Y21"
    )
    port map (
      ADR0 => UUT_N79_0,
      ADR1 => UUT_delay_count_mux0000_0_125_0,
      ADR2 => VCC,
      ADR3 => UUT_delay_count_and0000_0,
      O => UUT_delay_count_mux0000_0_145_O_pack_1
    );
  UUT_in_i2c_mux000093_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux000093_6645,
      O => UUT_in_i2c_mux000093_0
    );
  UUT_in_i2c_mux000093_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000035_pack_1,
      O => UUT_Dir_mux000035_2544
    );
  UUT_Dir_mux000035 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X21Y49"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_N32_0,
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_in_i2c_mux000078,
      O => UUT_Dir_mux000035_pack_1
    );
  UUT_in_i2c_mux0000190_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000190_6669,
      O => UUT_in_i2c_mux0000190_0
    );
  UUT_in_i2c_mux0000190_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000122_O_pack_1,
      O => UUT_in_i2c_mux0000122_O
    );
  UUT_in_i2c_mux0000122 : X_LUT4
    generic map(
      INIT => X"FF75",
      LOC => "SLICE_X21Y51"
    )
    port map (
      ADR0 => UUT_N1111,
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_N37,
      O => UUT_in_i2c_mux0000122_O_pack_1
    );
  UUT_in_i2c_mux0000275_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000275_6693,
      O => UUT_in_i2c_mux0000275_0
    );
  UUT_in_i2c_mux0000275_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y32",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000266_O_pack_1,
      O => UUT_in_i2c_mux0000266_O
    );
  UUT_in_i2c_mux0000266 : X_LUT4
    generic map(
      INIT => X"5050",
      LOC => "SLICE_X24Y32"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2553,
      ADR1 => VCC,
      ADR2 => UUT_in_i2c_2430,
      ADR3 => VCC,
      O => UUT_in_i2c_mux0000266_O_pack_1
    );
  UUT_in_i2c_mux000099_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux000099_6717,
      O => UUT_in_i2c_mux000099_0
    );
  UUT_in_i2c_mux000099_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X19Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N22_pack_1,
      O => UUT_N22
    );
  UUT_out_i2cclk_mux0000275 : X_LUT4
    generic map(
      INIT => X"FFEF",
      LOC => "SLICE_X19Y55"
    )
    port map (
      ADR0 => UUT_out_i2cclk_mux0000258_0,
      ADR1 => UUT_out_i2cclk_mux0000227_0,
      ADR2 => UUT_in_i2c_and0000_0,
      ADR3 => UUT_out_i2cclk_mux0000210_0,
      O => UUT_N22_pack_1
    );
  UUT_in_i2c_mux0000287_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000287_6741,
      O => UUT_in_i2c_mux0000287_0
    );
  UUT_in_i2c_mux0000287_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y33",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000250_O_pack_1,
      O => UUT_in_i2c_mux0000250_O
    );
  UUT_in_i2c_mux0000250 : X_LUT4
    generic map(
      INIT => X"CC0C",
      LOC => "SLICE_X22Y33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_in_i2c_mux0000247_0,
      ADR2 => UUT_shiftReg_and0000_0,
      ADR3 => UUT_shiftReg_or0000,
      O => UUT_in_i2c_mux0000250_O_pack_1
    );
  UUT_in_i2c_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000314,
      O => UUT_in_i2c_DXMUX_6772
    );
  UUT_in_i2c_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000216_O_pack_1,
      O => UUT_in_i2c_mux0000216_O
    );
  UUT_in_i2c_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux000063_6573,
      O => UUT_in_i2c_SRINV_6757
    );
  UUT_in_i2c_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y49",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_in_i2c_CLKINV_6756
    );
  UUT_delay_count_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(11),
      O => UUT_delay_count_11_DXMUX_6807
    );
  UUT_delay_count_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(10),
      O => UUT_delay_count_11_DYMUX_6796
    );
  UUT_delay_count_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_11_CLKINV_6788
    );
  UUT_delay_count_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X32Y20"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count_or0000,
      ADR2 => UUT_delay_count_share0000(10),
      ADR3 => UUT_delay_count(10),
      O => UUT_delay_count_mux0000(10)
    );
  UUT_delay_count_13_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(13),
      O => UUT_delay_count_13_DXMUX_6841
    );
  UUT_delay_count_13_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(12),
      O => UUT_delay_count_13_DYMUX_6830
    );
  UUT_delay_count_13_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y21",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_13_CLKINV_6822
    );
  UUT_delay_count_mux0000_12_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X32Y21"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count(12),
      ADR2 => UUT_N17_0,
      ADR3 => UUT_delay_count_share0000(12),
      O => UUT_delay_count_mux0000(12)
    );
  UUT_delay_count_15_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(15),
      O => UUT_delay_count_15_DXMUX_6875
    );
  UUT_delay_count_15_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(14),
      O => UUT_delay_count_15_DYMUX_6864
    );
  UUT_delay_count_15_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_15_CLKINV_6856
    );
  UUT_delay_count_mux0000_14_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X32Y23"
    )
    port map (
      ADR0 => UUT_delay_count(14),
      ADR1 => UUT_N17_0,
      ADR2 => UUT_delay_count_share0000(14),
      ADR3 => UUT_N3_0,
      O => UUT_delay_count_mux0000(14)
    );
  UUT_shiftReg_0_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000247_6909,
      O => UUT_in_i2c_mux0000247_0
    );
  UUT_shiftReg_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_23,
      O => UUT_shiftReg_0_DYMUX_6899
    );
  UUT_shiftReg_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_9_8536,
      O => UUT_shiftReg_0_SRINV_6891
    );
  UUT_shiftReg_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y35",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_0_CLKINV_6890
    );
  UUT_shiftReg_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_2_6942,
      O => UUT_shiftReg_mux0000_3_2_0
    );
  UUT_shiftReg_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_1_22,
      O => UUT_shiftReg_1_DYMUX_6933
    );
  UUT_shiftReg_1_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_1_8_F5MUX_4800,
      O => UUT_shiftReg_1_SRINV_6925
    );
  UUT_shiftReg_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y34",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_1_CLKINV_6924
    );
  UUT_shiftReg_3_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_5_3_6975,
      O => UUT_shiftReg_mux0000_5_3_0
    );
  UUT_shiftReg_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_32,
      O => UUT_shiftReg_3_DYMUX_6966
    );
  UUT_shiftReg_3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_14_5742,
      O => UUT_shiftReg_3_SRINV_6958
    );
  UUT_shiftReg_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X23Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_3_CLKINV_6957
    );
  UUT_shiftReg_4_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => N67,
      O => N67_0
    );
  UUT_shiftReg_4_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_4_22,
      O => UUT_shiftReg_4_DYMUX_6998
    );
  UUT_shiftReg_4_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_4_8_F5MUX_4825,
      O => UUT_shiftReg_4_SRINV_6990
    );
  UUT_shiftReg_4_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y29",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_4_CLKINV_6989
    );
  UUT_shiftReg_6_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => N99,
      O => N99_0
    );
  UUT_shiftReg_6_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_6_27,
      O => UUT_shiftReg_6_DYMUX_7032
    );
  UUT_shiftReg_6_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_6_11_8553,
      O => UUT_shiftReg_6_SRINV_7024
    );
  UUT_shiftReg_6_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X22Y30",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_shiftReg_6_CLKINV_7023
    );
  UUT_writeCount_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(1),
      O => UUT_writeCount_1_DXMUX_7074
    );
  UUT_writeCount_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(0),
      O => UUT_writeCount_1_DYMUX_7063
    );
  UUT_writeCount_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y7",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_1_CLKINV_7055
    );
  UUT_writeCount_mux0000_0_Q : X_LUT4
    generic map(
      INIT => X"F3AA",
      LOC => "SLICE_X16Y7"
    )
    port map (
      ADR0 => N18_0,
      ADR1 => UUT_N26_0,
      ADR2 => N19_0,
      ADR3 => UUT_delay_count_or0001,
      O => UUT_writeCount_mux0000(0)
    );
  UUT_writeCount_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(3),
      O => UUT_writeCount_3_DXMUX_7108
    );
  UUT_writeCount_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(2),
      O => UUT_writeCount_3_DYMUX_7097
    );
  UUT_writeCount_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y0",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_3_CLKINV_7089
    );
  UUT_writeCount_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y0"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount(2),
      ADR3 => UUT_writeCount_share0000(2),
      O => UUT_writeCount_mux0000(2)
    );
  UUT_writeCount_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(5),
      O => UUT_writeCount_5_DXMUX_7142
    );
  UUT_writeCount_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(4),
      O => UUT_writeCount_5_DYMUX_7131
    );
  UUT_writeCount_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y2",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_5_CLKINV_7123
    );
  UUT_writeCount_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y2"
    )
    port map (
      ADR0 => UUT_writeCount(4),
      ADR1 => UUT_N11,
      ADR2 => UUT_N31,
      ADR3 => UUT_writeCount_share0000(4),
      O => UUT_writeCount_mux0000(4)
    );
  UUT_writeCount_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(7),
      O => UUT_writeCount_7_DXMUX_7176
    );
  UUT_writeCount_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(6),
      O => UUT_writeCount_7_DYMUX_7165
    );
  UUT_writeCount_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y3",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_7_CLKINV_7157
    );
  UUT_writeCount_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y3"
    )
    port map (
      ADR0 => UUT_writeCount(6),
      ADR1 => UUT_N11,
      ADR2 => UUT_N31,
      ADR3 => UUT_writeCount_share0000(6),
      O => UUT_writeCount_mux0000(6)
    );
  UUT_prevClk_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_prevClk_mux0000,
      O => UUT_prevClk_DYMUX_7198
    );
  UUT_prevClk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_prevClk_CLKINV_7189
    );
  UUT_prevClk_mux00001 : X_LUT4
    generic map(
      INIT => X"EE88",
      LOC => "SLICE_X20Y39"
    )
    port map (
      ADR0 => UUT_ClkEdge(0),
      ADR1 => UUT_prevClk_2652,
      ADR2 => VCC,
      ADR3 => UUT_ClkEdge(1),
      O => UUT_prevClk_mux0000
    );
  UUT_ClkRisingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ClkRisingEdge_and00001,
      O => UUT_ClkRisingEdge_DYMUX_7226
    );
  UUT_ClkRisingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_prevClk_2652,
      O => UUT_ClkRisingEdge_SRINV_7216
    );
  UUT_ClkRisingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ClkRisingEdge_CLKINV_7215
    );
  UUT_pstate_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => N77,
      O => N77_0
    );
  UUT_pstate_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000(7),
      O => UUT_pstate_2_DYMUX_7249
    );
  UUT_pstate_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_pstate_2_CLKINV_7241
    );
  UUT_pstate_mux0000_7_Q : X_LUT4
    generic map(
      INIT => X"FACC",
      LOC => "SLICE_X27Y39"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1137_0,
      ADR1 => N33_0,
      ADR2 => N58_0,
      ADR3 => UUT_pstate(2),
      O => UUT_pstate_mux0000(7)
    );
  UUT_delay_count_0_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X28Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000_0_1_7274,
      O => UUT_delay_count_0_DYMUX_7277
    );
  UUT_delay_count_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => N14,
      O => UUT_delay_count_0_SRINV_7267
    );
  UUT_delay_count_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_0_CLKINV_7266
    );
  UUT_delay_count_1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_or000032_7309,
      O => UUT_shiftReg_or000032_0
    );
  UUT_delay_count_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X28Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(1),
      O => UUT_delay_count_1_DYMUX_7300
    );
  UUT_delay_count_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y20",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_1_CLKINV_7292
    );
  UUT_delay_count_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X28Y20"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(1),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_N17_0,
      ADR3 => UUT_delay_count(1),
      O => UUT_delay_count_mux0000(1)
    );
  UUT_delay_count_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(3),
      O => UUT_delay_count_3_DXMUX_7342
    );
  UUT_delay_count_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(2),
      O => UUT_delay_count_3_DYMUX_7331
    );
  UUT_delay_count_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y17",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_3_CLKINV_7323
    );
  UUT_delay_count_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X32Y17"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count(2),
      ADR2 => UUT_delay_count_share0000(2),
      ADR3 => UUT_delay_count_or0000,
      O => UUT_delay_count_mux0000(2)
    );
  UUT_delay_count_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(5),
      O => UUT_delay_count_5_DXMUX_7376
    );
  UUT_delay_count_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(4),
      O => UUT_delay_count_5_DYMUX_7365
    );
  UUT_delay_count_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y16",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_5_CLKINV_7357
    );
  UUT_delay_count_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X32Y16"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count(4),
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_delay_count_share0000(4),
      O => UUT_delay_count_mux0000(4)
    );
  UUT_delay_count_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(7),
      O => UUT_delay_count_7_DXMUX_7410
    );
  UUT_delay_count_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(6),
      O => UUT_delay_count_7_DYMUX_7399
    );
  UUT_delay_count_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y18",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_7_CLKINV_7391
    );
  UUT_delay_count_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X32Y18"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count(6),
      ADR2 => UUT_delay_count_share0000(6),
      ADR3 => UUT_delay_count_or0000,
      O => UUT_delay_count_mux0000(6)
    );
  UUT_delay_count_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(9),
      O => UUT_delay_count_9_DXMUX_7444
    );
  UUT_delay_count_9_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X32Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_mux0000(8),
      O => UUT_delay_count_9_DYMUX_7433
    );
  UUT_delay_count_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X32Y19",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_delay_count_9_CLKINV_7425
    );
  UUT_delay_count_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X32Y19"
    )
    port map (
      ADR0 => UUT_delay_count(8),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_N17_0,
      ADR3 => UUT_delay_count_share0000(8),
      O => UUT_delay_count_mux0000(8)
    );
  UUT_ack_count_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(11),
      O => UUT_ack_count_11_DXMUX_7478
    );
  UUT_ack_count_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(10),
      O => UUT_ack_count_11_DYMUX_7467
    );
  UUT_ack_count_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y61",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_11_CLKINV_7459
    );
  UUT_ack_count_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y61"
    )
    port map (
      ADR0 => UUT_ack_count(10),
      ADR1 => UUT_N16_0,
      ADR2 => UUT_N21_0,
      ADR3 => UUT_ack_count_share0000(10),
      O => UUT_ack_count_mux0000(10)
    );
  UUT_ack_count_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(7),
      O => UUT_ack_count_7_DXMUX_7512
    );
  UUT_ack_count_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X18Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(1),
      O => UUT_ack_count_7_DYMUX_7501
    );
  UUT_ack_count_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X18Y59",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_7_CLKINV_7493
    );
  UUT_ack_count_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X18Y59"
    )
    port map (
      ADR0 => UUT_N16_0,
      ADR1 => UUT_ack_count_share0000(1),
      ADR2 => UUT_N21_0,
      ADR3 => UUT_ack_count(1),
      O => UUT_ack_count_mux0000(1)
    );
  UUT_ack_count_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(3),
      O => UUT_ack_count_3_DXMUX_7546
    );
  UUT_ack_count_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X17Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(2),
      O => UUT_ack_count_3_DYMUX_7535
    );
  UUT_ack_count_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X17Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_3_CLKINV_7527
    );
  UUT_ack_count_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X17Y54"
    )
    port map (
      ADR0 => UUT_N21_0,
      ADR1 => UUT_N16_0,
      ADR2 => UUT_ack_count(2),
      ADR3 => UUT_ack_count_share0000(2),
      O => UUT_ack_count_mux0000(2)
    );
  UUT_ack_count_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(5),
      O => UUT_ack_count_5_DXMUX_7580
    );
  UUT_ack_count_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(4),
      O => UUT_ack_count_5_DYMUX_7569
    );
  UUT_ack_count_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y58",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_5_CLKINV_7561
    );
  UUT_ack_count_mux0000_4_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y58"
    )
    port map (
      ADR0 => UUT_N20,
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count_share0000(4),
      ADR3 => UUT_N21_0,
      O => UUT_ack_count_mux0000(4)
    );
  UUT_ack_count_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(9),
      O => UUT_ack_count_9_DXMUX_7614
    );
  UUT_ack_count_9_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ack_count_mux0000(8),
      O => UUT_ack_count_9_DYMUX_7603
    );
  UUT_ack_count_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y60",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ack_count_9_CLKINV_7595
    );
  UUT_ack_count_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y60"
    )
    port map (
      ADR0 => UUT_N16_0,
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_N21_0,
      ADR3 => UUT_ack_count_share0000(8),
      O => UUT_ack_count_mux0000(8)
    );
  UUT_writeCount_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(11),
      O => UUT_writeCount_11_DXMUX_7648
    );
  UUT_writeCount_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(10),
      O => UUT_writeCount_11_DYMUX_7637
    );
  UUT_writeCount_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y4",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_11_CLKINV_7629
    );
  UUT_writeCount_mux0000_10_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X14Y4"
    )
    port map (
      ADR0 => UUT_writeCount(10),
      ADR1 => UUT_writeCount_share0000(10),
      ADR2 => UUT_N31,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(10)
    );
  UUT_writeCount_13_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(13),
      O => UUT_writeCount_13_DXMUX_7682
    );
  UUT_writeCount_13_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X14Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(12),
      O => UUT_writeCount_13_DYMUX_7671
    );
  UUT_writeCount_13_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X14Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_13_CLKINV_7663
    );
  UUT_writeCount_mux0000_12_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X14Y6"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(12),
      ADR1 => UUT_N31,
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(12),
      O => UUT_writeCount_mux0000(12)
    );
  UUT_writeCount_21_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(21),
      O => UUT_writeCount_21_DXMUX_7716
    );
  UUT_writeCount_21_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(20),
      O => UUT_writeCount_21_DYMUX_7705
    );
  UUT_writeCount_21_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y10",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_21_CLKINV_7697
    );
  UUT_writeCount_mux0000_20_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y10"
    )
    port map (
      ADR0 => UUT_writeCount(20),
      ADR1 => UUT_N31,
      ADR2 => UUT_writeCount_share0000(20),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(20)
    );
  UUT_writeCount_15_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(15),
      O => UUT_writeCount_15_DXMUX_7750
    );
  UUT_writeCount_15_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(14),
      O => UUT_writeCount_15_DYMUX_7739
    );
  UUT_writeCount_15_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y6",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_15_CLKINV_7731
    );
  UUT_writeCount_mux0000_14_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y6"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount(14),
      ADR3 => UUT_writeCount_share0000(14),
      O => UUT_writeCount_mux0000(14)
    );
  UUT_writeCount_23_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(23),
      O => UUT_writeCount_23_DXMUX_7784
    );
  UUT_writeCount_23_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(22),
      O => UUT_writeCount_23_DYMUX_7773
    );
  UUT_writeCount_23_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y11",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_23_CLKINV_7765
    );
  UUT_writeCount_mux0000_22_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y11"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_writeCount(22),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount_share0000(22),
      O => UUT_writeCount_mux0000(22)
    );
  UUT_writeCount_30_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(30),
      O => UUT_writeCount_30_DYMUX_7802
    );
  UUT_writeCount_30_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y14",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_30_CLKINV_7794
    );
  UUT_writeCount_mux0000_30_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y14"
    )
    port map (
      ADR0 => UUT_writeCount(30),
      ADR1 => UUT_N11,
      ADR2 => UUT_N31,
      ADR3 => UUT_writeCount_share0000(30),
      O => UUT_writeCount_mux0000(30)
    );
  UUT_writeCount_17_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(17),
      O => UUT_writeCount_17_DXMUX_7836
    );
  UUT_writeCount_17_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(16),
      O => UUT_writeCount_17_DYMUX_7825
    );
  UUT_writeCount_17_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y8",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_17_CLKINV_7817
    );
  UUT_writeCount_mux0000_16_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X16Y8"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_writeCount(16),
      ADR2 => UUT_writeCount_share0000(16),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(16)
    );
  UUT_writeCount_25_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(25),
      O => UUT_writeCount_25_DXMUX_7870
    );
  UUT_writeCount_25_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(24),
      O => UUT_writeCount_25_DYMUX_7859
    );
  UUT_writeCount_25_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y13",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_25_CLKINV_7851
    );
  UUT_writeCount_mux0000_24_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y13"
    )
    port map (
      ADR0 => UUT_writeCount(24),
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount_share0000(24),
      ADR3 => UUT_N31,
      O => UUT_writeCount_mux0000(24)
    );
  UUT_writeCount_19_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(19),
      O => UUT_writeCount_19_DXMUX_7904
    );
  UUT_writeCount_19_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(18),
      O => UUT_writeCount_19_DYMUX_7893
    );
  UUT_writeCount_19_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y9",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_19_CLKINV_7885
    );
  UUT_writeCount_mux0000_18_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y9"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_writeCount(18),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount_share0000(18),
      O => UUT_writeCount_mux0000(18)
    );
  UUT_writeCount_27_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(27),
      O => UUT_writeCount_27_DXMUX_7938
    );
  UUT_writeCount_27_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(26),
      O => UUT_writeCount_27_DYMUX_7927
    );
  UUT_writeCount_27_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y12",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_27_CLKINV_7919
    );
  UUT_writeCount_mux0000_26_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X16Y12"
    )
    port map (
      ADR0 => UUT_writeCount(26),
      ADR1 => UUT_writeCount_share0000(26),
      ADR2 => UUT_N11,
      ADR3 => UUT_N31,
      O => UUT_writeCount_mux0000(26)
    );
  UUT_writeCount_29_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(29),
      O => UUT_writeCount_29_DXMUX_7972
    );
  UUT_writeCount_29_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_writeCount_mux0000(28),
      O => UUT_writeCount_29_DYMUX_7961
    );
  UUT_writeCount_29_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_writeCount_29_CLKINV_7953
    );
  UUT_writeCount_mux0000_28_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y15"
    )
    port map (
      ADR0 => UUT_writeCount(28),
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount_share0000(28),
      ADR3 => UUT_N31,
      O => UUT_writeCount_mux0000(28)
    );
  sSW_2_and00001 : X_LUT4
    generic map(
      INIT => X"1100",
      LOC => "SLICE_X24Y54"
    )
    port map (
      ADR0 => sSW(0),
      ADR1 => sSW(1),
      ADR2 => VCC,
      ADR3 => sSW(2),
      O => sSW_2_and0000
    );
  sSW_2_and00011 : X_LUT4
    generic map(
      INIT => X"4400",
      LOC => "SLICE_X24Y56"
    )
    port map (
      ADR0 => sSW(2),
      ADR1 => sSW(0),
      ADR2 => VCC,
      ADR3 => sSW(1),
      O => sSW_2_and0001
    );
  sSW_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => sSW(0),
      O => sSW_1_DXMUX_8024
    );
  sSW_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => SW_3_INBUF,
      O => sSW_1_DYMUX_8019
    );
  sSW_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y57",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2470,
      O => sSW_1_CLKINV_8017
    );
  N51_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => N51,
      O => N51_0
    );
  N51_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000062_8042,
      O => UUT_Dir_mux000062_0
    );
  UUT_Dir_mux000062 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X25Y23"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_delay_count(2),
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_delay_count(0),
      O => UUT_Dir_mux000062_8042
    );
  sSW_2_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => sSW_2_DYMUX_8061
    );
  sSW_2_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => sSW_2_and0000,
      O => sSW_2_SRINV_8059
    );
  sSW_2_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2470,
      O => sSW_2_CLKINV_8058
    );
  sSW_2_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => sSW_2_and0001,
      O => sSW_2_CEINV_8057
    );
  sSW_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X24Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => sSW_3_DYMUX_8074
    );
  sSW_3_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => sSW_3_or0000,
      O => sSW_3_SRINV_8072
    );
  sSW_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X24Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2470,
      O => sSW_3_CLKINV_8071
    );
  N73_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => N73,
      O => N73_0
    );
  N73_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y24",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux000057_8093,
      O => UUT_Dir_mux000057_0
    );
  UUT_Dir_mux000057 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X27Y24"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => UUT_delay_count(7),
      ADR2 => UUT_delay_count(9),
      ADR3 => UUT_delay_count(6),
      O => UUT_Dir_mux000057_8093
    );
  N21_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N21,
      O => N21_0
    );
  N21_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N97,
      O => N97_0
    );
  UUT_counter_mux0000_4_20_SW0 : X_LUT4
    generic map(
      INIT => X"FFFB",
      LOC => "SLICE_X17Y40"
    )
    port map (
      ADR0 => UUT_counter(3),
      ADR1 => UUT_counter(4),
      ADR2 => UUT_counter(2),
      ADR3 => UUT_counter(1),
      O => N97
    );
  UUT_nstate_cmp_eq0005_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0005,
      O => UUT_nstate_cmp_eq0005_0
    );
  UUT_nstate_cmp_eq0005_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux00009_8140,
      O => UUT_out_i2cclk_mux00009_0
    );
  UUT_out_i2cclk_mux00009 : X_LUT4
    generic map(
      INIT => X"F2F0",
      LOC => "SLICE_X21Y50"
    )
    port map (
      ADR0 => UUT_N41_0,
      ADR1 => UUT_N32_0,
      ADR2 => UUT_nstate_cmp_eq0006_0,
      ADR3 => UUT_nstate_cmp_eq0015,
      O => UUT_out_i2cclk_mux00009_8140
    );
  N101_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => N101,
      O => N101_0
    );
  N101_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X23Y31",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N104,
      O => UUT_N104_0
    );
  UUT_N1041 : X_LUT4
    generic map(
      INIT => X"00C0",
      LOC => "SLICE_X23Y31"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ClkRisingEdge_2447,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_N104
    );
  UUT_N66_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N66,
      O => UUT_N66_0
    );
  UUT_N66_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X14Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N2119_8188,
      O => UUT_N2119_0
    );
  UUT_N2119 : X_LUT4
    generic map(
      INIT => X"7F00",
      LOC => "SLICE_X14Y54"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_ack_count(6),
      O => UUT_N2119_8188
    );
  UUT_out_i2cclk_mux0000210_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux0000210_8220,
      O => UUT_out_i2cclk_mux0000210_0
    );
  UUT_out_i2cclk_mux0000210_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y55",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N2170_8212,
      O => UUT_N2170_0
    );
  UUT_N2170 : X_LUT4
    generic map(
      INIT => X"7754",
      LOC => "SLICE_X18Y55"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_ack_count(7),
      O => UUT_N2170_8212
    );
  CLK_sI2C_Clk_cmp_eq00007_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y37",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq00007_8232,
      O => CLK_sI2C_Clk_cmp_eq00007_0
    );
  CLK_sI2C_Clk_cmp_eq00007 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X28Y37"
    )
    port map (
      ADR0 => CLK_clk_div(5),
      ADR1 => CLK_clk_div(6),
      ADR2 => CLK_clk_div(7),
      ADR3 => CLK_clk_div(4),
      O => CLK_sI2C_Clk_cmp_eq00007_8232
    );
  UUT_N112_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N112,
      O => UUT_N112_0
    );
  UUT_N112_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000203_8247,
      O => UUT_Dir_mux0000203_0
    );
  UUT_Dir_mux0000203 : X_LUT4
    generic map(
      INIT => X"4040",
      LOC => "SLICE_X24Y50"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => UUT_ack_count(5),
      ADR3 => VCC,
      O => UUT_Dir_mux0000203_8247
    );
  UUT_delay_count_and0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y26",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_delay_count_and0000,
      O => UUT_delay_count_and0000_0
    );
  UUT_Dir_mux0000128 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X25Y26"
    )
    port map (
      ADR0 => UUT_delay_count_or0001,
      ADR1 => UUT_Dir_mux0000122_2573,
      ADR2 => UUT_shiftReg_cmp_eq0002_0,
      ADR3 => UUT_N33_0,
      O => UUT_Dir_mux0000128_8273
    );
  N91_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => N91,
      O => N91_0
    );
  N91_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y54",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_mux0000227_8297,
      O => UUT_Dir_mux0000227_0
    );
  UUT_Dir_mux0000227 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "SLICE_X21Y54"
    )
    port map (
      ADR0 => UUT_ack_count(3),
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count(6),
      ADR3 => UUT_N37,
      O => UUT_Dir_mux0000227_8297
    );
  UUT_counter_mux0000_4_7_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_mux0000_4_7_8328,
      O => UUT_counter_mux0000_4_7_0
    );
  UUT_counter_mux0000_4_7_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0012,
      O => UUT_nstate_cmp_eq0012_0
    );
  UUT_Dir_mux0000521 : X_LUT4
    generic map(
      INIT => X"5050",
      LOC => "SLICE_X21Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => VCC,
      O => UUT_nstate_cmp_eq0012
    );
  N31_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y23",
      PATHPULSE => 798 ps
    )
    port map (
      I => N31,
      O => N31_0
    );
  UUT_shiftReg_cmp_eq00032_SW0 : X_LUT4
    generic map(
      INIT => X"FAFA",
      LOC => "SLICE_X27Y23"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => VCC,
      ADR2 => UUT_delay_count(4),
      ADR3 => VCC,
      O => N31
    );
  UUT_nstate_FFd3_In1_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd3_In1_8364,
      O => UUT_nstate_FFd3_In1_0
    );
  UUT_nstate_FFd3_In1_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y47",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_pstate_mux0000_7_1175_8355,
      O => UUT_pstate_mux0000_7_1175_0
    );
  UUT_pstate_mux0000_7_1175 : X_LUT4
    generic map(
      INIT => X"0051",
      LOC => "SLICE_X22Y47"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => sSW(3),
      ADR2 => CLK_sI2C_Clk_2470,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_pstate_mux0000_7_1175_8355
    );
  UUT_nstate_cmp_eq0011_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0011,
      O => UUT_nstate_cmp_eq0011_0
    );
  UUT_nstate_cmp_eq0011_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y48",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_mux000050_8381,
      O => UUT_out_i2cclk_mux000050_0
    );
  UUT_out_i2cclk_mux000050 : X_LUT4
    generic map(
      INIT => X"FFEE",
      LOC => "SLICE_X21Y48"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd2_2441,
      O => UUT_out_i2cclk_mux000050_8381
    );
  CLK_sI2C_Clk_DYMUX : X_INV
    generic map(
      LOC => "SLICE_X28Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2470,
      O => CLK_sI2C_Clk_DYMUX_8398
    );
  CLK_sI2C_Clk_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => CLK_sI2C_Clk_CLKINV_8396
    );
  CLK_sI2C_Clk_CEINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000_0,
      O => CLK_sI2C_Clk_CEINV_8395
    );
  N16_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => N16,
      O => N16_0
    );
  N16_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X15Y52",
      PATHPULSE => 798 ps
    )
    port map (
      I => N126,
      O => N126_0
    );
  UUT_ack_count_mux0000_0_45_SW1 : X_LUT4
    generic map(
      INIT => X"FFFD",
      LOC => "SLICE_X15Y52"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2553,
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_nstate_FFd1_2439,
      O => N126
    );
  CLK_sI2C_Clk_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq0000,
      O => CLK_sI2C_Clk_cmp_eq0000_0
    );
  CLK_sI2C_Clk_cmp_eq0000_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X28Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_cmp_eq000016_pack_1,
      O => CLK_sI2C_Clk_cmp_eq000016_2666
    );
  CLK_sI2C_Clk_cmp_eq000016 : X_LUT4
    generic map(
      INIT => X"0040",
      LOC => "SLICE_X28Y36"
    )
    port map (
      ADR0 => CLK_clk_div(1),
      ADR1 => CLK_clk_div(2),
      ADR2 => CLK_clk_div(3),
      ADR3 => CLK_clk_div(0),
      O => CLK_sI2C_Clk_cmp_eq000016_pack_1
    );
  UUT_ClkEdge_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ClkEdge(0),
      O => UUT_ClkEdge_1_DXMUX_8463
    );
  UUT_ClkEdge_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => CLK_sI2C_Clk_2470,
      O => UUT_ClkEdge_1_DYMUX_8458
    );
  UUT_ClkEdge_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X20Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ClkEdge_1_CLKINV_8456
    );
  UUT_shiftReg_mux0000_3_8_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_3_8,
      O => UUT_shiftReg_mux0000_3_8_0
    );
  UUT_nstate_FFd1_In0 : X_LUT4
    generic map(
      INIT => X"1000",
      LOC => "SLICE_X22Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_nstate_FFd4_2442,
      ADR2 => UUT_nstate_cmp_eq0001_0,
      ADR3 => UUT_N40,
      O => UUT_nstate_FFd1_In0_8480
    );
  N120_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => N120,
      O => N120_0
    );
  N120_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X17Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => N89,
      O => N89_0
    );
  UUT_ack_count_mux0000_0_68_SW0 : X_LUT4
    generic map(
      INIT => X"FFBF",
      LOC => "SLICE_X17Y51"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_nstate_cmp_eq0015,
      ADR2 => UUT_ClkRisingEdge_2447,
      ADR3 => UUT_N32_0,
      O => N89
    );
  UUT_shiftReg_mux0000_0_9_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X22Y36",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_mux0000_0_2_pack_1,
      O => UUT_shiftReg_mux0000_0_2
    );
  UUT_shiftReg_mux0000_0_21 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X22Y36"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => out_i2c,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd1_2439,
      O => UUT_shiftReg_mux0000_0_2_pack_1
    );
  UUT_shiftReg_mux0000_6_11 : X_LUT4
    generic map(
      INIT => X"FF80",
      LOC => "SLICE_X22Y31"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_3_8_0,
      ADR1 => UUT_shiftReg_cmp_eq0002_0,
      ADR2 => UUT_shiftReg_and0000_0,
      ADR3 => N101_0,
      O => UUT_shiftReg_mux0000_6_11_8553
    );
  N18_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y15",
      PATHPULSE => 798 ps
    )
    port map (
      I => N18,
      O => N18_0
    );
  UUT_delay_count_mux0000_0_SW0 : X_LUT4
    generic map(
      INIT => X"F8C8",
      LOC => "SLICE_X24Y15"
    )
    port map (
      ADR0 => UUT_delay_count_or0000,
      ADR1 => UUT_delay_count(0),
      ADR2 => UUT_N107,
      ADR3 => UUT_ClkFallingEdge_2553,
      O => N14
    );
  UUT_nstate_cmp_eq0006_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_cmp_eq0006,
      O => UUT_nstate_cmp_eq0006_0
    );
  UUT_nstate_cmp_eq0006_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X20Y51",
      PATHPULSE => 798 ps
    )
    port map (
      I => N113,
      O => N113_0
    );
  UUT_in_i2c_mux000034_SW0 : X_LUT4
    generic map(
      INIT => X"FFF7",
      LOC => "SLICE_X20Y51"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N113
    );
  UUT_in_i2c_mux0000158_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_mux0000158_8632,
      O => UUT_in_i2c_mux0000158_0
    );
  UUT_in_i2c_mux0000158_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X18Y50",
      PATHPULSE => 798 ps
    )
    port map (
      I => N95,
      O => N95_0
    );
  UUT_in_i2c_mux0000211_SW0 : X_LUT4
    generic map(
      INIT => X"5155",
      LOC => "SLICE_X18Y50"
    )
    port map (
      ADR0 => UUT_N41_0,
      ADR1 => UUT_N100,
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(6),
      O => N95
    );
  UUT_ClkFallingEdge_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X21Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => UUT_ClkFallingEdge_DYMUX_8642
    );
  UUT_ClkFallingEdge_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_ClkFallingEdge_not0001,
      O => UUT_ClkFallingEdge_SRINV_8640
    );
  UUT_ClkFallingEdge_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X21Y39",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_ClkFallingEdge_CLKINV_8639
    );
  UUT_shiftReg_cmp_eq0000_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y27",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_shiftReg_cmp_eq0000,
      O => UUT_shiftReg_cmp_eq0000_0
    );
  UUT_shiftReg_cmp_eq00001 : X_LUT4
    generic map(
      INIT => X"000C",
      LOC => "SLICE_X25Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_N42,
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_delay_count(0),
      O => UUT_shiftReg_cmp_eq0000
    );
  N33_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N33,
      O => N33_0
    );
  N33_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X31Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N39,
      O => N39_0
    );
  UUT_pstate_mux0000_5_SW0 : X_LUT4
    generic map(
      INIT => X"2000",
      LOC => "SLICE_X31Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd3_2440,
      O => N39
    );
  N37_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N37,
      O => N37_0
    );
  N37_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => N40,
      O => N40_0
    );
  UUT_pstate_mux0000_5_SW1 : X_LUT4
    generic map(
      INIT => X"A880",
      LOC => "SLICE_X27Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR2 => UUT_nstate_FFd2_2441,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N40
    );
  UUT_counter_0_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_mux0000_4_47,
      O => UUT_counter_0_DXMUX_8735
    );
  UUT_counter_0_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N62_pack_1,
      O => UUT_N62
    );
  UUT_counter_0_SRINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_counter_mux0000_4_20_5871,
      O => UUT_counter_0_SRINV_8719
    );
  UUT_counter_0_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X16Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => FPGA_Clk_BUFGP,
      O => UUT_counter_0_CLKINV_8718
    );
  UUT_N106_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_N106,
      O => UUT_N106_0
    );
  UUT_N106_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X25Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => N36,
      O => N36_0
    );
  UUT_pstate_mux0000_6_SW0 : X_LUT4
    generic map(
      INIT => X"FFBF",
      LOC => "SLICE_X25Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => N36
    );
  UUT_nstate_FFd3_In14_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X24Y41",
      PATHPULSE => 798 ps
    )
    port map (
      I => N128_pack_1,
      O => N128
    );
  UUT_nstate_FFd3_In14_SW0 : X_LUT4
    generic map(
      INIT => X"FFEE",
      LOC => "SLICE_X24Y41"
    )
    port map (
      ADR0 => UUT_pstate(3),
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => VCC,
      ADR3 => UUT_pstate(2),
      O => N128_pack_1
    );
  UUT_Madd_counter_addsub0000_cy_2_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X13Y38",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Madd_counter_addsub0000_cy(2),
      O => UUT_Madd_counter_addsub0000_cy_2_0
    );
  UUT_Madd_counter_addsub0000_cy_2_11 : X_LUT4
    generic map(
      INIT => X"8800",
      LOC => "SLICE_X13Y38"
    )
    port map (
      ADR0 => UUT_counter(0),
      ADR1 => UUT_counter(1),
      ADR2 => VCC,
      ADR3 => UUT_counter(2),
      O => UUT_Madd_counter_addsub0000_cy(2)
    );
  UUT_nstate_FFd2_In27_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X21Y53",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd2_In11_pack_1,
      O => UUT_nstate_FFd2_In11_2670
    );
  UUT_nstate_FFd2_In11 : X_LUT4
    generic map(
      INIT => X"BFFF",
      LOC => "SLICE_X21Y53"
    )
    port map (
      ADR0 => UUT_ack_count(1),
      ADR1 => UUT_nstate_FFd4_2442,
      ADR2 => UUT_ack_count(6),
      ADR3 => UUT_ack_count(4),
      O => UUT_nstate_FFd2_In11_pack_1
    );
  UUT_nstate_FFd4_In59_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X27Y40",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_nstate_FFd4_In59_8833,
      O => UUT_nstate_FFd4_In59_0
    );
  UUT_nstate_FFd4_In59 : X_LUT4
    generic map(
      INIT => X"CC5D",
      LOC => "SLICE_X27Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd3_2440,
      O => UUT_nstate_FFd4_In59_8833
    );
  UUT_delay_count_4_rt_1 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X35Y19"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_4_rt
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_3_Q : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X35Y20"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_delay_count(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(3)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_5_1 : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X35Y21"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_delay_count(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_5_1_4407
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_7_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X35Y22"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(7)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_1_Q : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X31Y17"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_delay_count(5),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(1)
    );
  UUT_delay_count_8_rt_2 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X31Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_cy_3_G
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0011",
      LOC => "SLICE_X31Y19"
    )
    port map (
      ADR0 => UUT_delay_count(13),
      ADR1 => UUT_delay_count(14),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(15),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(5)
    );
  UUT_Dir_mux000025_F : X_LUT4
    generic map(
      INIT => X"0457",
      LOC => "SLICE_X22Y49"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N146
    );
  UUT_Dir_mux0000164_F : X_LUT4
    generic map(
      INIT => X"0044",
      LOC => "SLICE_X25Y50"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_nstate_FFd4_2442,
      ADR2 => VCC,
      ADR3 => UUT_nstate_FFd2_2441,
      O => N136
    );
  UUT_ack_count_mux0000_0_10_F : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X16Y52"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_ack_count_cmp_eq0000_0,
      ADR2 => UUT_nstate_cmp_eq0007,
      ADR3 => VCC,
      O => N148
    );
  UUT_pstate_mux0000_7_1167_SW0_F : X_LUT4
    generic map(
      INIT => X"F5F1",
      LOC => "SLICE_X24Y39"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1175_0,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd1_2439,
      O => N81
    );
  UUT_pstate_mux0000_7_1167_SW1_F : X_LUT4
    generic map(
      INIT => X"DDCD",
      LOC => "SLICE_X24Y38"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1175_0,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_N40,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N83
    );
  UUT_shiftReg_mux0000_1_8_F : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X24Y35"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_shiftReg(0),
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => VCC,
      O => N144
    );
  UUT_shiftReg_mux0000_4_8_F : X_LUT4
    generic map(
      INIT => X"8080",
      LOC => "SLICE_X24Y30"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_shiftReg(3),
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => VCC,
      O => N142
    );
  UUT_nstate_FFd4_In14_F : X_LUT4
    generic map(
      INIT => X"1100",
      LOC => "SLICE_X23Y44"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => CLK_sI2C_Clk_2470,
      ADR2 => VCC,
      ADR3 => sSW(3),
      O => N150
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y7"
    )
    port map (
      ADR0 => UUT_writeCount(2),
      ADR1 => UUT_writeCount(24),
      ADR2 => UUT_writeCount(22),
      ADR3 => UUT_writeCount(23),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(5)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_7_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y8"
    )
    port map (
      ADR0 => UUT_writeCount(0),
      ADR1 => UUT_writeCount(29),
      ADR2 => UUT_writeCount(28),
      ADR3 => UUT_writeCount(30),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(7)
    );
  UUT_delay_count_15_rt : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X33Y22"
    )
    port map (
      ADR0 => UUT_delay_count(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_15_rt_4035
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X25Y53"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_ack_count(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(1)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_3_Q : X_LUT4
    generic map(
      INIT => X"C000",
      LOC => "SLICE_X25Y54"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_ack_count(7),
      ADR3 => UUT_ack_count(6),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(3)
    );
  UUT_nstate_cmp_eq0001_SW0_SW0 : X_LUT4
    generic map(
      INIT => X"EEEE",
      LOC => "SLICE_X25Y55"
    )
    port map (
      ADR0 => UUT_ack_count(9),
      ADR1 => UUT_ack_count(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => N45
    );
  CLK_clk_div_7_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X29Y38"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => CLK_clk_div(7),
      O => CLK_clk_div_7_rt_4312
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q : X_LUT4
    generic map(
      INIT => X"0033",
      LOC => "SLICE_X31Y13"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(4),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(3),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_1_Q_3259
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_3_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X31Y14"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_3_Q
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X31Y15"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_delay_count(11),
      ADR2 => UUT_delay_count(9),
      ADR3 => UUT_delay_count(12),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_5_Q_3322
    );
  UUT_ack_count_11_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y61"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(11),
      O => UUT_ack_count_11_rt_3561
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_1_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X15Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(4),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(5),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_1_1_3588
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_3_1 : X_LUT4
    generic map(
      INIT => X"0033",
      LOC => "SLICE_X15Y54"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(10),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(11),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_3_1_3618
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_1_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y5"
    )
    port map (
      ADR0 => UUT_writeCount(11),
      ADR1 => UUT_writeCount(12),
      ADR2 => UUT_writeCount(6),
      ADR3 => UUT_writeCount(10),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(1)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_3_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y6"
    )
    port map (
      ADR0 => UUT_writeCount(18),
      ADR1 => UUT_writeCount(17),
      ADR2 => UUT_writeCount(16),
      ADR3 => UUT_writeCount(4),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(3)
    );
  UUT_counter_mux0000_4_7 : X_LUT4
    generic map(
      INIT => X"0004",
      LOC => "SLICE_X21Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_counter_mux0000_4_7_8328
    );
  UUT_nstate_FFd3_In1 : X_LUT4
    generic map(
      INIT => X"EEEE",
      LOC => "SLICE_X22Y47"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_nstate_FFd4_2442,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_nstate_FFd3_In1_8364
    );
  UUT_nstate_Out51 : X_LUT4
    generic map(
      INIT => X"1000",
      LOC => "SLICE_X21Y48"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd2_2441,
      O => UUT_nstate_cmp_eq0011
    );
  CLK_sI2C_Clk : X_FF
    generic map(
      LOC => "SLICE_X28Y39",
      INIT => '0'
    )
    port map (
      I => CLK_sI2C_Clk_DYMUX_8398,
      CE => CLK_sI2C_Clk_CEINV_8395,
      CLK => CLK_sI2C_Clk_CLKINV_8396,
      SET => GND,
      RST => GND,
      O => CLK_sI2C_Clk_2470
    );
  UUT_ack_count_cmp_eq0000_SW0 : X_LUT4
    generic map(
      INIT => X"FAFA",
      LOC => "SLICE_X15Y52"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => VCC,
      O => N16
    );
  CLK_sI2C_Clk_cmp_eq000017 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X28Y36"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CLK_sI2C_Clk_cmp_eq00007_0,
      ADR2 => VCC,
      ADR3 => CLK_sI2C_Clk_cmp_eq000016_2666,
      O => CLK_sI2C_Clk_cmp_eq0000
    );
  UUT_ClkEdge_0 : X_FF
    generic map(
      LOC => "SLICE_X20Y38",
      INIT => '0'
    )
    port map (
      I => UUT_ClkEdge_1_DYMUX_8458,
      CE => VCC,
      CLK => UUT_ClkEdge_1_CLKINV_8456,
      SET => GND,
      RST => GND,
      O => UUT_ClkEdge(0)
    );
  UUT_ClkEdge_1 : X_FF
    generic map(
      LOC => "SLICE_X20Y38",
      INIT => '0'
    )
    port map (
      I => UUT_ClkEdge_1_DXMUX_8463,
      CE => VCC,
      CLK => UUT_ClkEdge_1_CLKINV_8456,
      SET => GND,
      RST => GND,
      O => UUT_ClkEdge(1)
    );
  UUT_counter_mux0000_4_2 : X_LUT4
    generic map(
      INIT => X"FFFC",
      LOC => "SLICE_X16Y41"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => N120_0,
      O => UUT_N62_pack_1
    );
  UUT_Madd_writeCount_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"0F0F",
      LOC => "SLICE_X17Y0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(0),
      ADR3 => VCC,
      O => UUT_Madd_writeCount_share0000_lut(0)
    );
  UUT_nstate_FFd4_In28 : X_LUT4
    generic map(
      INIT => X"E0F0",
      LOC => "SLICE_X24Y40"
    )
    port map (
      ADR0 => UUT_pstate(3),
      ADR1 => UUT_pstate(4),
      ADR2 => UUT_N106_0,
      ADR3 => UUT_pstate(2),
      O => UUT_nstate_FFd4_In28_O_pack_1
    );
  UUT_in_i2c_mux0000216 : X_LUT4
    generic map(
      INIT => X"AAA8",
      LOC => "SLICE_X20Y49"
    )
    port map (
      ADR0 => UUT_in_i2c_2430,
      ADR1 => UUT_in_i2c_mux000099_0,
      ADR2 => UUT_in_i2c_mux0000190_0,
      ADR3 => UUT_in_i2c_mux000093_0,
      O => UUT_in_i2c_mux0000216_O_pack_1
    );
  UUT_shiftReg_mux0000_0_231 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X22Y35"
    )
    port map (
      ADR0 => UUT_N25_0,
      ADR1 => UUT_shiftReg(0),
      ADR2 => UUT_N15_0,
      ADR3 => UUT_shiftReg(1),
      O => UUT_shiftReg_mux0000_0_23
    );
  UUT_shiftReg_mux0000_1_221 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X22Y34"
    )
    port map (
      ADR0 => UUT_N15_0,
      ADR1 => UUT_N25_0,
      ADR2 => UUT_shiftReg(2),
      ADR3 => UUT_shiftReg(1),
      O => UUT_shiftReg_mux0000_1_22
    );
  UUT_shiftReg_mux0000_3_321 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X23Y30"
    )
    port map (
      ADR0 => UUT_shiftReg(3),
      ADR1 => UUT_shiftReg(4),
      ADR2 => UUT_N25_0,
      ADR3 => UUT_N15_0,
      O => UUT_shiftReg_mux0000_3_32
    );
  UUT_shiftReg_mux0000_4_221 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X22Y29"
    )
    port map (
      ADR0 => UUT_N15_0,
      ADR1 => UUT_N25_0,
      ADR2 => UUT_shiftReg(5),
      ADR3 => UUT_shiftReg(4),
      O => UUT_shiftReg_mux0000_4_22
    );
  UUT_shiftReg_mux0000_6_271 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X22Y30"
    )
    port map (
      ADR0 => UUT_N25_0,
      ADR1 => UUT_shiftReg(7),
      ADR2 => UUT_N15_0,
      ADR3 => UUT_shiftReg(6),
      O => UUT_shiftReg_mux0000_6_27
    );
  UUT_ClkRisingEdge_and000011 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X21Y38"
    )
    port map (
      ADR0 => UUT_ClkEdge(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ClkEdge(0),
      O => UUT_ClkRisingEdge_and00001
    );
  UUT_delay_count_mux0000_0_1 : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X28Y15"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count_share0000(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_mux0000_0_1_7274
    );
  UUT_Dir_mux000092 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X23Y48"
    )
    port map (
      ADR0 => UUT_delay_count_or0000,
      ADR1 => UUT_Dir_mux000035_2544,
      ADR2 => UUT_Dir_mux000025,
      ADR3 => UUT_Dir_mux000083_0,
      O => UUT_Dir_mux000092_O_pack_1
    );
  UUT_shiftReg_mux0000_0_257_SW3 : X_LUT4
    generic map(
      INIT => X"FAF2",
      LOC => "SLICE_X23Y29"
    )
    port map (
      ADR0 => UUT_shiftReg(5),
      ADR1 => UUT_ClkFallingEdge_2553,
      ADR2 => UUT_shiftReg_mux0000_5_3_0,
      ADR3 => UUT_shiftReg_mux0000_0_210_0,
      O => UUT_shiftReg_mux0000_0_257_SW3_O_pack_1
    );
  UUT_shiftReg_mux0000_0_257_SW1 : X_LUT4
    generic map(
      INIT => X"AA22",
      LOC => "SLICE_X23Y28"
    )
    port map (
      ADR0 => UUT_shiftReg(7),
      ADR1 => UUT_ClkFallingEdge_2553,
      ADR2 => VCC,
      ADR3 => UUT_shiftReg_mux0000_0_210_0,
      O => UUT_shiftReg_mux0000_0_257_SW1_O_pack_1
    );
  UUT_shiftReg_mux0000_2_SW0 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X23Y33"
    )
    port map (
      ADR0 => UUT_shiftReg(3),
      ADR1 => UUT_shiftReg(1),
      ADR2 => UUT_N25_0,
      ADR3 => UUT_N104_0,
      O => UUT_shiftReg_mux0000_2_SW0_O_pack_1
    );
  UUT_nstate_FFd1_In33 : X_LUT4
    generic map(
      INIT => X"1B1B",
      LOC => "SLICE_X22Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_cmp_eq0000_2545,
      ADR2 => UUT_nstate_cmp_eq0005_0,
      ADR3 => VCC,
      O => UUT_nstate_FFd1_In33_O_pack_1
    );
  UUT_out_i2cclk_mux000097 : X_LUT4
    generic map(
      INIT => X"8A88",
      LOC => "SLICE_X20Y54"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0007,
      ADR1 => UUT_out_i2cclk_mux000080_0,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0000_cy_3_1,
      ADR3 => UUT_N22,
      O => UUT_out_i2cclk_mux000097_O_pack_1
    );
  UUT_Dir_mux000025_G : X_LUT4
    generic map(
      INIT => X"04FF",
      LOC => "SLICE_X22Y49"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N147
    );
  UUT_Dir_mux0000164_G : X_LUT4
    generic map(
      INIT => X"0200",
      LOC => "SLICE_X25Y50"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_nstate_FFd4_2442,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd2_2441,
      O => N137
    );
  UUT_ack_count_mux0000_0_10_G : X_LUT4
    generic map(
      INIT => X"C0D5",
      LOC => "SLICE_X16Y52"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_ack_count_cmp_eq0000_0,
      ADR2 => UUT_nstate_cmp_eq0007,
      ADR3 => UUT_nstate_FFd2_2441,
      O => N149
    );
  UUT_pstate_mux0000_7_1167_SW0_G : X_LUT4
    generic map(
      INIT => X"CDDD",
      LOC => "SLICE_X24Y39"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1175_0,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_N40,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N82
    );
  UUT_pstate_mux0000_7_1167_SW1_G : X_LUT4
    generic map(
      INIT => X"DDDD",
      LOC => "SLICE_X24Y38"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1175_0,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N84
    );
  UUT_shiftReg_mux0000_1_8_G : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X24Y35"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_shiftReg_cmp_eq0002_0,
      ADR3 => UUT_shiftReg_and0000_0,
      O => N145
    );
  UUT_shiftReg_mux0000_4_8_G : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X24Y30"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_shiftReg_cmp_eq0002_0,
      ADR3 => UUT_shiftReg_and0000_0,
      O => N143
    );
  UUT_nstate_FFd2_In771_G : X_LUT4
    generic map(
      INIT => X"D000",
      LOC => "SLICE_X25Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => UUT_nstate_FFd2_2441,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => N153
    );
  UUT_counter_mux0000_0_G : X_LUT4
    generic map(
      INIT => X"BFAA",
      LOC => "SLICE_X12Y38"
    )
    port map (
      ADR0 => UUT_N62,
      ADR1 => UUT_counter(3),
      ADR2 => UUT_Madd_counter_addsub0000_cy_2_0,
      ADR3 => UUT_nstate_FFd1_2439,
      O => N139
    );
  UUT_counter_mux0000_1_G : X_LUT4
    generic map(
      INIT => X"E2C0",
      LOC => "SLICE_X12Y39"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_counter(3),
      ADR2 => UUT_N62,
      ADR3 => UUT_nstate_cmp_eq0012_0,
      O => N133
    );
  UUT_counter_mux0000_2_G : X_LUT4
    generic map(
      INIT => X"FF2A",
      LOC => "SLICE_X13Y39"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_counter(1),
      ADR2 => UUT_counter(0),
      ADR3 => UUT_N62,
      O => N141
    );
  UUT_counter_mux0000_3_G : X_LUT4
    generic map(
      INIT => X"FF44",
      LOC => "SLICE_X15Y39"
    )
    port map (
      ADR0 => UUT_counter(0),
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => VCC,
      ADR3 => UUT_N62,
      O => N135
    );
  UUT_nstate_FFd4_In14_G : X_LUT4
    generic map(
      INIT => X"0004",
      LOC => "SLICE_X23Y44"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_nstate_cmp_eq0001_0,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd1_2439,
      O => N151
    );
  CLK_clk_div_1 : X_SFF
    generic map(
      LOC => "SLICE_X29Y35",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_0_DYMUX_4167,
      CE => VCC,
      CLK => CLK_clk_div_0_CLKINV_4150,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_0_SRINV_4151,
      O => CLK_clk_div(1)
    );
  CLK_clk_div_7 : X_SFF
    generic map(
      LOC => "SLICE_X29Y38",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_6_DYMUX_4317,
      CE => VCC,
      CLK => CLK_clk_div_6_CLKINV_4303,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_6_SRINV_4304,
      O => CLK_clk_div(7)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_0_Q : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X15Y5"
    )
    port map (
      ADR0 => UUT_writeCount(8),
      ADR1 => VCC,
      ADR2 => UUT_writeCount(7),
      ADR3 => UUT_writeCount(9),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(0)
    );
  UUT_Madd_ack_count_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X17Y56"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Madd_ack_count_share0000_lut(0)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_2_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X25Y54"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(2)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_4_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X25Y55"
    )
    port map (
      ADR0 => UUT_ack_count(11),
      ADR1 => UUT_ack_count(10),
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_ack_count(9),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(4)
    );
  CLK_Mcount_clk_div_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X29Y35"
    )
    port map (
      ADR0 => CLK_clk_div(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_Mcount_clk_div_lut(0)
    );
  CLK_clk_div_0 : X_SFF
    generic map(
      LOC => "SLICE_X29Y35",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_0_DXMUX_4187,
      CE => VCC,
      CLK => CLK_clk_div_0_CLKINV_4150,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_0_SRINV_4151,
      O => CLK_clk_div(0)
    );
  CLK_clk_div_3 : X_SFF
    generic map(
      LOC => "SLICE_X29Y36",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_2_DYMUX_4222,
      CE => VCC,
      CLK => CLK_clk_div_2_CLKINV_4200,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_2_SRINV_4201,
      O => CLK_clk_div(3)
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"0F0F",
      LOC => "SLICE_X25Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(1),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0000_lut(0)
    );
  UUT_delay_count_2_rt : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X31Y13"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(2),
      ADR3 => VCC,
      O => UUT_delay_count_2_rt_3272
    );
  UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X31Y14"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_delay_count(5),
      O => UUT_Mcompar_delay_count_cmp_lt0000_lut_2_Q_3306
    );
  UUT_delay_count_8_rt : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X31Y15"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(8),
      O => UUT_delay_count_8_rt_3336
    );
  UUT_in_i2c_mux000099 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X19Y55"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_cmp_eq0007,
      ADR2 => VCC,
      ADR3 => UUT_N22,
      O => UUT_in_i2c_mux000099_6717
    );
  UUT_in_i2c_mux0000287 : X_LUT4
    generic map(
      INIT => X"FEFC",
      LOC => "SLICE_X22Y33"
    )
    port map (
      ADR0 => UUT_shiftReg_cmp_eq0000_0,
      ADR1 => UUT_N46,
      ADR2 => UUT_in_i2c_mux0000250_O,
      ADR3 => UUT_in_i2c_mux0000275_0,
      O => UUT_in_i2c_mux0000287_6741
    );
  UUT_in_i2c_mux00003141 : X_LUT4
    generic map(
      INIT => X"FCF8",
      LOC => "SLICE_X20Y49"
    )
    port map (
      ADR0 => UUT_N0,
      ADR1 => UUT_in_i2c_mux0000287_0,
      ADR2 => UUT_in_i2c_mux0000216_O,
      ADR3 => UUT_nstate_cmp_eq0011_0,
      O => UUT_in_i2c_mux0000314
    );
  UUT_in_i2c : X_SFF
    generic map(
      LOC => "SLICE_X20Y49",
      INIT => '1'
    )
    port map (
      I => UUT_in_i2c_DXMUX_6772,
      CE => VCC,
      CLK => UUT_in_i2c_CLKINV_6756,
      SET => GND,
      RST => GND,
      SSET => UUT_in_i2c_SRINV_6757,
      SRST => GND,
      O => UUT_in_i2c_2430
    );
  UUT_delay_count_10 : X_FF
    generic map(
      LOC => "SLICE_X32Y20",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_11_DYMUX_6796,
      CE => VCC,
      CLK => UUT_delay_count_11_CLKINV_6788,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(10)
    );
  UUT_delay_count_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X32Y20"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_delay_count_share0000(11),
      ADR2 => UUT_delay_count(11),
      ADR3 => UUT_N17_0,
      O => UUT_delay_count_mux0000(11)
    );
  UUT_delay_count_11 : X_FF
    generic map(
      LOC => "SLICE_X32Y20",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_11_DXMUX_6807,
      CE => VCC,
      CLK => UUT_delay_count_11_CLKINV_6788,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(11)
    );
  UUT_delay_count_12 : X_FF
    generic map(
      LOC => "SLICE_X32Y21",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_13_DYMUX_6830,
      CE => VCC,
      CLK => UUT_delay_count_13_CLKINV_6822,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(12)
    );
  UUT_delay_count_mux0000_13_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X32Y21"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(13),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_delay_count(13),
      ADR3 => UUT_N17_0,
      O => UUT_delay_count_mux0000(13)
    );
  UUT_delay_count_13 : X_FF
    generic map(
      LOC => "SLICE_X32Y21",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_13_DXMUX_6841,
      CE => VCC,
      CLK => UUT_delay_count_13_CLKINV_6822,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(13)
    );
  UUT_delay_count_14 : X_FF
    generic map(
      LOC => "SLICE_X32Y23",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_15_DYMUX_6864,
      CE => VCC,
      CLK => UUT_delay_count_15_CLKINV_6856,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(14)
    );
  UUT_delay_count_mux0000_15_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X32Y23"
    )
    port map (
      ADR0 => UUT_N17_0,
      ADR1 => UUT_N3_0,
      ADR2 => UUT_delay_count_share0000(15),
      ADR3 => UUT_delay_count(15),
      O => UUT_delay_count_mux0000(15)
    );
  UUT_delay_count_15 : X_FF
    generic map(
      LOC => "SLICE_X32Y23",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_15_DXMUX_6875,
      CE => VCC,
      CLK => UUT_delay_count_15_CLKINV_6856,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(15)
    );
  UUT_shiftReg_0 : X_SFF
    generic map(
      LOC => "SLICE_X22Y35",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_0_DYMUX_6899,
      CE => VCC,
      CLK => UUT_shiftReg_0_CLKINV_6890,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_0_SRINV_6891,
      SRST => GND,
      O => UUT_shiftReg(0)
    );
  UUT_Madd_delay_count_share0000_lut_0_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X33Y15"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Madd_delay_count_share0000_lut(0)
    );
  UUT_nstate_FFd3_In3111 : X_LUT4
    generic map(
      INIT => X"0347",
      LOC => "SLICE_X25Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      O => UUT_nstate_FFd3_In311
    );
  UUT_nstate_FFd3 : X_SFF
    generic map(
      LOC => "SLICE_X25Y41",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd3_DXMUX_4772,
      CE => VCC,
      CLK => UUT_nstate_FFd3_CLKINV_4751,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd3_SRINV_4752,
      SRST => GND,
      O => UUT_nstate_FFd3_2440
    );
  UUT_nstate_FFd2 : X_SFF
    generic map(
      LOC => "SLICE_X25Y39",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd2_DXMUX_4856,
      CE => VCC,
      CLK => UUT_nstate_FFd2_CLKINV_4839,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd2_SRINV_4840,
      SRST => GND,
      O => UUT_nstate_FFd2_2441
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_0_1 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y53"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_ack_count(1),
      ADR3 => UUT_ack_count(3),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_0_1_3601
    );
  UUT_Mcompar_nstate_cmp_gt0000_lut_2_1 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y54"
    )
    port map (
      ADR0 => UUT_ack_count(9),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(8),
      ADR3 => UUT_ack_count(7),
      O => UUT_Mcompar_nstate_cmp_gt0000_lut_2_1_3634
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_2_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y6"
    )
    port map (
      ADR0 => UUT_writeCount(5),
      ADR1 => UUT_writeCount(14),
      ADR2 => UUT_writeCount(15),
      ADR3 => UUT_writeCount(13),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(2)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_4_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y7"
    )
    port map (
      ADR0 => UUT_writeCount(19),
      ADR1 => UUT_writeCount(20),
      ADR2 => UUT_writeCount(3),
      ADR3 => UUT_writeCount(21),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(4)
    );
  UUT_shiftReg_cmp_eq0001_wg_lut_6_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X15Y8"
    )
    port map (
      ADR0 => UUT_writeCount(1),
      ADR1 => UUT_writeCount(26),
      ADR2 => UUT_writeCount(25),
      ADR3 => UUT_writeCount(27),
      O => UUT_shiftReg_cmp_eq0001_wg_lut(6)
    );
  UUT_pstate_3 : X_FF
    generic map(
      LOC => "SLICE_X25Y38",
      INIT => '0'
    )
    port map (
      I => UUT_pstate_3_DXMUX_5114,
      CE => VCC,
      CLK => UUT_pstate_3_CLKINV_5099,
      SET => GND,
      RST => GND,
      O => UUT_pstate(3)
    );
  UUT_out_i2cclk_mux000018_SW0 : X_LUT4
    generic map(
      INIT => X"EFFF",
      LOC => "SLICE_X16Y55"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_N44,
      ADR3 => UUT_N38,
      O => N111
    );
  UUT_out_i2cclk_mux00003 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X16Y54"
    )
    port map (
      ADR0 => UUT_ack_count(7),
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_ack_count(9),
      ADR3 => UUT_out_i2cclk_mux00003_SW0_O,
      O => UUT_N32
    );
  UUT_ack_count_cmp_eq0000 : X_LUT4
    generic map(
      INIT => X"0010",
      LOC => "SLICE_X19Y52"
    )
    port map (
      ADR0 => UUT_N32_0,
      ADR1 => N16_0,
      ADR2 => UUT_N100,
      ADR3 => UUT_ack_count(6),
      O => UUT_ack_count_cmp_eq0000_5187
    );
  UUT_N2116 : X_LUT4
    generic map(
      INIT => X"7530",
      LOC => "SLICE_X14Y50"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count(5),
      ADR3 => UUT_in_i2c_mux000078,
      O => UUT_N2116_5211
    );
  UUT_N2140 : X_LUT4
    generic map(
      INIT => X"EF00",
      LOC => "SLICE_X14Y53"
    )
    port map (
      ADR0 => UUT_N2116_0,
      ADR1 => UUT_N2119_0,
      ADR2 => UUT_ack_count_and0023,
      ADR3 => UUT_nstate_cmp_eq0015,
      O => UUT_N2140_5235
    );
  UUT_N2181 : X_LUT4
    generic map(
      INIT => X"BBB0",
      LOC => "SLICE_X18Y56"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_ack_count(3),
      ADR3 => UUT_N2181_SW0_O,
      O => UUT_N2181_5259
    );
  UUT_Dir_mux0000230 : X_LUT4
    generic map(
      INIT => X"C8C0",
      LOC => "SLICE_X23Y50"
    )
    port map (
      ADR0 => UUT_Dir_mux0000164,
      ADR1 => UUT_Dir_mux0000227_0,
      ADR2 => UUT_Dir_mux0000205_O,
      ADR3 => UUT_Dir_mux0000178_0,
      O => UUT_Dir_mux0000230_5283
    );
  UUT_Dir_mux0000178 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X22Y50"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_ack_count(7),
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_N1111,
      O => UUT_Dir_mux0000178_5307
    );
  UUT_shiftReg_and00001 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X30Y21"
    )
    port map (
      ADR0 => UUT_delay_count(3),
      ADR1 => UUT_delay_count(2),
      ADR2 => UUT_shiftReg_cmp_eq00031_SW1_O,
      ADR3 => N25,
      O => UUT_shiftReg_and0000
    );
  UUT_ack_count_mux0000_0_45 : X_LUT4
    generic map(
      INIT => X"0004",
      LOC => "SLICE_X14Y52"
    )
    port map (
      ADR0 => N126_0,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_N37,
      ADR3 => UUT_ack_count_mux0000_0_45_SW0_O,
      O => UUT_ack_count_mux0000_0_45_5355
    );
  UUT_pstate_mux0000_7_1115 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X23Y40"
    )
    port map (
      ADR0 => UUT_Mcompar_nstate_cmp_gt0000_cy_4_Q,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR2 => UUT_nstate_cmp_eq0007,
      ADR3 => UUT_nstate_cmp_eq0014,
      O => UUT_pstate_mux0000_7_1115_5379
    );
  UUT_pstate_mux0000_7_1137 : X_LUT4
    generic map(
      INIT => X"FDEC",
      LOC => "SLICE_X22Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_pstate_mux0000_7_1115_0,
      ADR2 => UUT_nstate_FFd4_In62_2521,
      ADR3 => N117_0,
      O => UUT_pstate_mux0000_7_1137_5403
    );
  UUT_shiftReg_or00002 : X_LUT4
    generic map(
      INIT => X"22EF",
      LOC => "SLICE_X26Y23"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(7),
      ADR2 => UUT_shiftReg_or00002_SW0_O,
      ADR3 => UUT_delay_count(10),
      O => UUT_N79
    );
  UUT_out_i2cclk_mux000030 : X_LUT4
    generic map(
      INIT => X"F8F0",
      LOC => "SLICE_X20Y55"
    )
    port map (
      ADR0 => UUT_out_i2cclk_mux000018_O,
      ADR1 => UUT_nstate_cmp_eq0007,
      ADR2 => UUT_out_i2cclk_mux00009_0,
      ADR3 => UUT_out_i2cclk_2438,
      O => UUT_out_i2cclk_mux000030_5451
    );
  UUT_ack_count_mux0000_6_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X17Y55"
    )
    port map (
      ADR0 => UUT_N21_0,
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count_share0000(6),
      ADR3 => UUT_N20,
      O => UUT_ack_count_mux0000(6)
    );
  UUT_ack_count_6 : X_FF
    generic map(
      LOC => "SLICE_X17Y55",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_6_DXMUX_5480,
      CE => VCC,
      CLK => UUT_ack_count_6_CLKINV_5465,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(6)
    );
  UUT_out_i2cclk_mux000080 : X_LUT4
    generic map(
      INIT => X"C8C0",
      LOC => "SLICE_X18Y54"
    )
    port map (
      ADR0 => UUT_N44,
      ADR1 => UUT_in_i2c_and0000_0,
      ADR2 => UUT_in_i2c_cmp_eq0000,
      ADR3 => UUT_out_i2cclk_mux000064_O,
      O => UUT_out_i2cclk_mux000080_5505
    );
  CLK_clk_div_2 : X_SFF
    generic map(
      LOC => "SLICE_X29Y36",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_2_DXMUX_4239,
      CE => VCC,
      CLK => CLK_clk_div_2_CLKINV_4200,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_2_SRINV_4201,
      O => CLK_clk_div(2)
    );
  CLK_clk_div_5 : X_SFF
    generic map(
      LOC => "SLICE_X29Y37",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_4_DYMUX_4274,
      CE => VCC,
      CLK => CLK_clk_div_4_CLKINV_4252,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_4_SRINV_4253,
      O => CLK_clk_div(5)
    );
  CLK_clk_div_4 : X_SFF
    generic map(
      LOC => "SLICE_X29Y37",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_4_DXMUX_4291,
      CE => VCC,
      CLK => CLK_clk_div_4_CLKINV_4252,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_4_SRINV_4253,
      O => CLK_clk_div(4)
    );
  CLK_clk_div_6 : X_SFF
    generic map(
      LOC => "SLICE_X29Y38",
      INIT => '0'
    )
    port map (
      I => CLK_clk_div_6_DXMUX_4336,
      CE => VCC,
      CLK => CLK_clk_div_6_CLKINV_4303,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => CLK_clk_div_6_SRINV_4304,
      O => CLK_clk_div(6)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_0_1 : X_LUT4
    generic map(
      INIT => X"1111",
      LOC => "SLICE_X35Y19"
    )
    port map (
      ADR0 => UUT_delay_count(2),
      ADR1 => UUT_delay_count(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_0_1_4360
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_2_1_INV_0 : X_LUT4
    generic map(
      INIT => X"5555",
      LOC => "SLICE_X35Y20"
    )
    port map (
      ADR0 => UUT_delay_count(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_2_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_4_1_INV_0 : X_LUT4
    generic map(
      INIT => X"3333",
      LOC => "SLICE_X35Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut_4_1
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_6_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X35Y22"
    )
    port map (
      ADR0 => UUT_delay_count(12),
      ADR1 => UUT_delay_count(11),
      ADR2 => UUT_delay_count(13),
      ADR3 => UUT_delay_count(14),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(6)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_0_Q : X_LUT4
    generic map(
      INIT => X"0101",
      LOC => "SLICE_X31Y17"
    )
    port map (
      ADR0 => UUT_delay_count(4),
      ADR1 => UUT_delay_count(3),
      ADR2 => UUT_delay_count(2),
      ADR3 => VCC,
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(0)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_2_INV_0 : X_LUT4
    generic map(
      INIT => X"00FF",
      LOC => "SLICE_X31Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(7),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(2)
    );
  UUT_Mcompar_nstate_cmp_gt0002_lut_4_Q : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X31Y19"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(11),
      ADR2 => UUT_delay_count(10),
      ADR3 => UUT_delay_count(12),
      O => UUT_Mcompar_nstate_cmp_gt0002_lut(4)
    );
  UUT_ack_count_7 : X_FF
    generic map(
      LOC => "SLICE_X18Y59",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_7_DXMUX_7512,
      CE => VCC,
      CLK => UUT_ack_count_7_CLKINV_7493,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(7)
    );
  UUT_ack_count_2 : X_FF
    generic map(
      LOC => "SLICE_X17Y54",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_3_DYMUX_7535,
      CE => VCC,
      CLK => UUT_ack_count_3_CLKINV_7527,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(2)
    );
  UUT_ack_count_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X17Y54"
    )
    port map (
      ADR0 => UUT_N21_0,
      ADR1 => UUT_ack_count(3),
      ADR2 => UUT_ack_count_share0000(3),
      ADR3 => UUT_N20,
      O => UUT_ack_count_mux0000(3)
    );
  UUT_ack_count_3 : X_FF
    generic map(
      LOC => "SLICE_X17Y54",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_3_DXMUX_7546,
      CE => VCC,
      CLK => UUT_ack_count_3_CLKINV_7527,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(3)
    );
  UUT_ack_count_4 : X_FF
    generic map(
      LOC => "SLICE_X16Y58",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_5_DYMUX_7569,
      CE => VCC,
      CLK => UUT_ack_count_5_CLKINV_7561,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(4)
    );
  UUT_ack_count_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y58"
    )
    port map (
      ADR0 => UUT_N20,
      ADR1 => UUT_ack_count_share0000(5),
      ADR2 => UUT_N21_0,
      ADR3 => UUT_ack_count(5),
      O => UUT_ack_count_mux0000(5)
    );
  UUT_ack_count_5 : X_FF
    generic map(
      LOC => "SLICE_X16Y58",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_5_DXMUX_7580,
      CE => VCC,
      CLK => UUT_ack_count_5_CLKINV_7561,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(5)
    );
  UUT_ack_count_8 : X_FF
    generic map(
      LOC => "SLICE_X16Y60",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_9_DYMUX_7603,
      CE => VCC,
      CLK => UUT_ack_count_9_CLKINV_7595,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(8)
    );
  UUT_ack_count_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y60"
    )
    port map (
      ADR0 => UUT_N16_0,
      ADR1 => UUT_ack_count_share0000(9),
      ADR2 => UUT_N21_0,
      ADR3 => UUT_ack_count(9),
      O => UUT_ack_count_mux0000(9)
    );
  UUT_ack_count_9 : X_FF
    generic map(
      LOC => "SLICE_X16Y60",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_9_DXMUX_7614,
      CE => VCC,
      CLK => UUT_ack_count_9_CLKINV_7595,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(9)
    );
  UUT_writeCount_10 : X_FF
    generic map(
      LOC => "SLICE_X14Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_11_DYMUX_7637,
      CE => VCC,
      CLK => UUT_writeCount_11_CLKINV_7629,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(10)
    );
  UUT_writeCount_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X14Y4"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount(11),
      ADR3 => UUT_writeCount_share0000(11),
      O => UUT_writeCount_mux0000(11)
    );
  UUT_writeCount_11 : X_FF
    generic map(
      LOC => "SLICE_X14Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_11_DXMUX_7648,
      CE => VCC,
      CLK => UUT_writeCount_11_CLKINV_7629,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(11)
    );
  UUT_writeCount_12 : X_FF
    generic map(
      LOC => "SLICE_X14Y6",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_13_DYMUX_7671,
      CE => VCC,
      CLK => UUT_writeCount_13_CLKINV_7663,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(12)
    );
  UUT_writeCount_mux0000_13_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X14Y6"
    )
    port map (
      ADR0 => UUT_writeCount(13),
      ADR1 => UUT_N31,
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount_share0000(13),
      O => UUT_writeCount_mux0000(13)
    );
  UUT_writeCount_13 : X_FF
    generic map(
      LOC => "SLICE_X14Y6",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_13_DXMUX_7682,
      CE => VCC,
      CLK => UUT_writeCount_13_CLKINV_7663,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(13)
    );
  UUT_writeCount_20 : X_FF
    generic map(
      LOC => "SLICE_X16Y10",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_21_DYMUX_7705,
      CE => VCC,
      CLK => UUT_writeCount_21_CLKINV_7697,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(20)
    );
  UUT_writeCount_mux0000_21_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y10"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_writeCount_share0000(21),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(21),
      O => UUT_writeCount_mux0000(21)
    );
  UUT_writeCount_21 : X_FF
    generic map(
      LOC => "SLICE_X16Y10",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_21_DXMUX_7716,
      CE => VCC,
      CLK => UUT_writeCount_21_CLKINV_7697,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(21)
    );
  UUT_in_i2c_mux0000247 : X_LUT4
    generic map(
      INIT => X"D8D8",
      LOC => "SLICE_X22Y35"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2553,
      ADR1 => UUT_shiftReg(0),
      ADR2 => UUT_in_i2c_2430,
      ADR3 => VCC,
      O => UUT_in_i2c_mux0000247_6909
    );
  UUT_shiftReg_1 : X_SFF
    generic map(
      LOC => "SLICE_X22Y34",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_1_DYMUX_6933,
      CE => VCC,
      CLK => UUT_shiftReg_1_CLKINV_6924,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_1_SRINV_6925,
      SRST => GND,
      O => UUT_shiftReg(1)
    );
  UUT_shiftReg_mux0000_3_2 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X22Y34"
    )
    port map (
      ADR0 => UUT_ClkRisingEdge_2447,
      ADR1 => UUT_shiftReg(2),
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd1_2439,
      O => UUT_shiftReg_mux0000_3_2_6942
    );
  UUT_shiftReg_3 : X_SFF
    generic map(
      LOC => "SLICE_X23Y30",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_3_DYMUX_6966,
      CE => VCC,
      CLK => UUT_shiftReg_3_CLKINV_6957,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_3_SRINV_6958,
      SRST => GND,
      O => UUT_shiftReg(3)
    );
  UUT_shiftReg_mux0000_5_3 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "SLICE_X23Y30"
    )
    port map (
      ADR0 => UUT_shiftReg(4),
      ADR1 => UUT_ClkRisingEdge_2447,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_shiftReg_mux0000_5_3_6975
    );
  UUT_shiftReg_4 : X_SFF
    generic map(
      LOC => "SLICE_X22Y29",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_4_DYMUX_6998,
      CE => VCC,
      CLK => UUT_shiftReg_4_CLKINV_6989,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_4_SRINV_6990,
      SRST => GND,
      O => UUT_shiftReg(4)
    );
  UUT_shiftReg_mux0000_0_257_SW2 : X_LUT4
    generic map(
      INIT => X"FAF0",
      LOC => "SLICE_X22Y29"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_210_0,
      ADR1 => VCC,
      ADR2 => UUT_shiftReg_mux0000_5_3_0,
      ADR3 => UUT_shiftReg(5),
      O => N67
    );
  UUT_shiftReg_6 : X_SFF
    generic map(
      LOC => "SLICE_X22Y30",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_6_DYMUX_7032,
      CE => VCC,
      CLK => UUT_shiftReg_6_CLKINV_7023,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_6_SRINV_7024,
      SRST => GND,
      O => UUT_shiftReg(6)
    );
  UUT_shiftReg_mux0000_7_5_SW0 : X_LUT4
    generic map(
      INIT => X"4000",
      LOC => "SLICE_X22Y30"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => UUT_ClkRisingEdge_2447,
      ADR3 => UUT_shiftReg(6),
      O => N99
    );
  UUT_writeCount_0 : X_FF
    generic map(
      LOC => "SLICE_X16Y7",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_1_DYMUX_7063,
      CE => VCC,
      CLK => UUT_writeCount_1_CLKINV_7055,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(0)
    );
  UUT_writeCount_mux0000_1_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y7"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(1),
      ADR1 => UUT_N31,
      ADR2 => UUT_writeCount(1),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(1)
    );
  UUT_writeCount_1 : X_FF
    generic map(
      LOC => "SLICE_X16Y7",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_1_DXMUX_7074,
      CE => VCC,
      CLK => UUT_writeCount_1_CLKINV_7055,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(1)
    );
  UUT_writeCount_2 : X_FF
    generic map(
      LOC => "SLICE_X16Y0",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_3_DYMUX_7097,
      CE => VCC,
      CLK => UUT_writeCount_3_CLKINV_7089,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(2)
    );
  UUT_writeCount_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X16Y0"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(3),
      ADR1 => UUT_writeCount(3),
      ADR2 => UUT_N31,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(3)
    );
  UUT_counter_4 : X_FF
    generic map(
      LOC => "SLICE_X12Y38",
      INIT => '0'
    )
    port map (
      I => UUT_counter_4_DXMUX_4888,
      CE => VCC,
      CLK => UUT_counter_4_CLKINV_4872,
      SET => GND,
      RST => GND,
      O => UUT_counter(4)
    );
  UUT_counter_3 : X_FF
    generic map(
      LOC => "SLICE_X12Y39",
      INIT => '0'
    )
    port map (
      I => UUT_counter_3_DXMUX_4919,
      CE => VCC,
      CLK => UUT_counter_3_CLKINV_4902,
      SET => GND,
      RST => GND,
      O => UUT_counter(3)
    );
  UUT_counter_2 : X_FF
    generic map(
      LOC => "SLICE_X13Y39",
      INIT => '0'
    )
    port map (
      I => UUT_counter_2_DXMUX_4950,
      CE => VCC,
      CLK => UUT_counter_2_CLKINV_4934,
      SET => GND,
      RST => GND,
      O => UUT_counter(2)
    );
  UUT_counter_1 : X_FF
    generic map(
      LOC => "SLICE_X15Y39",
      INIT => '0'
    )
    port map (
      I => UUT_counter_1_DXMUX_4981,
      CE => VCC,
      CLK => UUT_counter_1_CLKINV_4964,
      SET => GND,
      RST => GND,
      O => UUT_counter(1)
    );
  UUT_shiftReg_mux0000_0_257_SW0 : X_LUT4
    generic map(
      INIT => X"CCC8",
      LOC => "SLICE_X23Y32"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_28_2476,
      ADR1 => UUT_shiftReg(7),
      ADR2 => UUT_nstate_cmp_eq0014,
      ADR3 => UUT_counter_mux0000_4_7_0,
      O => N64
    );
  UUT_Dir_mux000083 : X_LUT4
    generic map(
      INIT => X"FD00",
      LOC => "SLICE_X24Y24"
    )
    port map (
      ADR0 => UUT_N33_0,
      ADR1 => UUT_Dir_mux000057_0,
      ADR2 => UUT_Dir_mux000062_0,
      ADR3 => UUT_delay_count_or0001,
      O => UUT_Dir_mux000083_5055
    );
  UUT_pstate_mux0000_5_Q : X_LUT4
    generic map(
      INIT => X"FCB8",
      LOC => "SLICE_X26Y38"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1137_0,
      ADR1 => UUT_pstate(4),
      ADR2 => N39_0,
      ADR3 => UUT_pstate_mux0000_7_11104_SW2_O,
      O => UUT_pstate_mux0000(5)
    );
  UUT_pstate_4 : X_FF
    generic map(
      LOC => "SLICE_X26Y38",
      INIT => '0'
    )
    port map (
      I => UUT_pstate_4_DXMUX_5084,
      CE => VCC,
      CLK => UUT_pstate_4_CLKINV_5069,
      SET => GND,
      RST => GND,
      O => UUT_pstate(4)
    );
  UUT_pstate_mux0000_6_Q : X_LUT4
    generic map(
      INIT => X"AF33",
      LOC => "SLICE_X25Y38"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_1137_0,
      ADR1 => N36_0,
      ADR2 => UUT_pstate_mux0000_7_11104_SW1_O,
      ADR3 => UUT_pstate(3),
      O => UUT_pstate_mux0000(6)
    );
  UUT_N21151 : X_LUT4
    generic map(
      INIT => X"FFEC",
      LOC => "SLICE_X19Y54"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_N2170_0,
      ADR2 => UUT_N21130_O,
      ADR3 => UUT_N2181_0,
      O => UUT_N21151_5529
    );
  UUT_N21180 : X_LUT4
    generic map(
      INIT => X"FEFC",
      LOC => "SLICE_X18Y53"
    )
    port map (
      ADR0 => UUT_counter_mux0000_4_7_0,
      ADR1 => UUT_N2140_0,
      ADR2 => UUT_N217_O,
      ADR3 => UUT_N21151_0,
      O => UUT_N21
    );
  UUT_in_i2c_and00001 : X_LUT4
    generic map(
      INIT => X"0003",
      LOC => "SLICE_X14Y55"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(8),
      ADR2 => UUT_N37,
      ADR3 => UUT_ack_count(0),
      O => UUT_in_i2c_and0000
    );
  UUT_Dir_mux00002431 : X_LUT4
    generic map(
      INIT => X"ECEC",
      LOC => "SLICE_X23Y48"
    )
    port map (
      ADR0 => UUT_Dir_2431,
      ADR1 => UUT_Dir_mux0000230_0,
      ADR2 => UUT_Dir_mux000092_O,
      ADR3 => VCC,
      O => UUT_Dir_mux0000243
    );
  UUT_Dir : X_SFF
    generic map(
      LOC => "SLICE_X23Y48",
      INIT => '1'
    )
    port map (
      I => UUT_Dir_DXMUX_5608,
      CE => VCC,
      CLK => UUT_Dir_CLKINV_5591,
      SET => GND,
      RST => GND,
      SSET => UUT_Dir_SRINV_5592,
      SRST => GND,
      O => UUT_Dir_2431
    );
  UUT_pstate_mux0000_7_1137_SW0 : X_LUT4
    generic map(
      INIT => X"00CC",
      LOC => "SLICE_X16Y40"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => VCC,
      ADR3 => UUT_nstate_cmp_eq0000_2545,
      O => N117
    );
  UUT_shiftReg_mux0000_0_30 : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X27Y25"
    )
    port map (
      ADR0 => N31_0,
      ADR1 => N73_0,
      ADR2 => UUT_delay_count(6),
      ADR3 => UUT_N0,
      O => UUT_shiftReg_mux0000_0_30_5658
    );
  UUT_writeCount_mux0000_8_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y5"
    )
    port map (
      ADR0 => UUT_writeCount(8),
      ADR1 => UUT_writeCount_share0000(8),
      ADR2 => UUT_N31,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(8)
    );
  UUT_writeCount_8 : X_FF
    generic map(
      LOC => "SLICE_X16Y5",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_8_DXMUX_5687,
      CE => VCC,
      CLK => UUT_writeCount_8_CLKINV_5671,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(8)
    );
  UUT_writeCount_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y4"
    )
    port map (
      ADR0 => UUT_writeCount(9),
      ADR1 => UUT_writeCount_share0000(9),
      ADR2 => UUT_N31,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(9)
    );
  UUT_shiftReg_mux0000_0_210 : X_LUT4
    generic map(
      INIT => X"FFEE",
      LOC => "SLICE_X22Y32"
    )
    port map (
      ADR0 => UUT_counter_mux0000_4_7_0,
      ADR1 => UUT_nstate_cmp_eq0014,
      ADR2 => VCC,
      ADR3 => UUT_shiftReg_mux0000_0_28_2476,
      O => UUT_shiftReg_mux0000_0_210_5919
    );
  UUT_shiftReg_mux0000_0_211 : X_LUT4
    generic map(
      INIT => X"BFFF",
      LOC => "SLICE_X25Y22"
    )
    port map (
      ADR0 => N51_0,
      ADR1 => UUT_shiftReg_cmp_eq0001,
      ADR2 => UUT_N42,
      ADR3 => UUT_N33_0,
      O => UUT_N26
    );
  UUT_shiftReg_mux0000_0_311 : X_LUT4
    generic map(
      INIT => X"EAAA",
      LOC => "SLICE_X24Y27"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2553,
      ADR1 => UUT_N33_0,
      ADR2 => UUT_Dir_mux0000122_2573,
      ADR3 => UUT_shiftReg_cmp_eq0001,
      O => UUT_N29
    );
  UUT_shiftReg_mux0000_0_232 : X_LUT4
    generic map(
      INIT => X"CCC4",
      LOC => "SLICE_X24Y26"
    )
    port map (
      ADR0 => UUT_shiftReg_and0000_0,
      ADR1 => UUT_N0,
      ADR2 => UUT_shiftReg_or0000,
      ADR3 => UUT_shiftReg_mux0000_0_218_O,
      O => UUT_shiftReg_mux0000_0_232_5991
    );
  UUT_shiftReg_mux0000_0_316 : X_LUT4
    generic map(
      INIT => X"A2A2",
      LOC => "SLICE_X26Y25"
    )
    port map (
      ADR0 => UUT_N0,
      ADR1 => UUT_shiftReg_and0000_0,
      ADR2 => UUT_shiftReg_or0000,
      ADR3 => VCC,
      O => UUT_shiftReg_mux0000_0_316_6015
    );
  UUT_shiftReg_mux0000_0_328 : X_LUT4
    generic map(
      INIT => X"FEF0",
      LOC => "SLICE_X24Y29"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_316_0,
      ADR1 => UUT_nstate_cmp_eq0011_0,
      ADR2 => UUT_shiftReg_mux0000_0_39_2581,
      ADR3 => UUT_ClkFallingEdge_2553,
      O => UUT_N25
    );
  UUT_shiftReg_mux0000_0_257 : X_LUT4
    generic map(
      INIT => X"AFAE",
      LOC => "SLICE_X22Y28"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_210_0,
      ADR1 => UUT_shiftReg_mux0000_0_215_2583,
      ADR2 => UUT_ClkFallingEdge_2553,
      ADR3 => UUT_shiftReg_mux0000_0_232_0,
      O => UUT_N15
    );
  UUT_out_i2cclk_mux0000227 : X_LUT4
    generic map(
      INIT => X"A2AA",
      LOC => "SLICE_X18Y57"
    )
    port map (
      ADR0 => UUT_ack_count(7),
      ADR1 => UUT_ack_count(2),
      ADR2 => UUT_out_i2cclk_mux0000218_O,
      ADR3 => UUT_ack_count(1),
      O => UUT_out_i2cclk_mux0000227_6087
    );
  UUT_shiftReg_mux0000_5_0 : X_LUT4
    generic map(
      INIT => X"A8A0",
      LOC => "SLICE_X24Y28"
    )
    port map (
      ADR0 => UUT_shiftReg(6),
      ADR1 => UUT_ClkFallingEdge_2553,
      ADR2 => UUT_shiftReg_mux0000_0_39_2581,
      ADR3 => UUT_shiftReg_mux0000_0_328_SW0_O,
      O => UUT_shiftReg_mux0000_5_0_6306
    );
  UUT_shiftReg_cmp_eq00031 : X_LUT4
    generic map(
      INIT => X"0001",
      LOC => "SLICE_X30Y20"
    )
    port map (
      ADR0 => UUT_delay_count(3),
      ADR1 => UUT_delay_count(8),
      ADR2 => UUT_delay_count(11),
      ADR3 => N25,
      O => UUT_N33
    );
  UUT_nstate_FFd1_In421 : X_LUT4
    generic map(
      INIT => X"DC50",
      LOC => "SLICE_X22Y40"
    )
    port map (
      ADR0 => N77_0,
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => UUT_N106_0,
      ADR3 => UUT_nstate_FFd1_In33_O,
      O => UUT_nstate_FFd1_In42
    );
  UUT_nstate_FFd1 : X_SFF
    generic map(
      LOC => "SLICE_X22Y40",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd1_DXMUX_6361,
      CE => VCC,
      CLK => UUT_nstate_FFd1_CLKINV_6344,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd1_SRINV_6345,
      SRST => GND,
      O => UUT_nstate_FFd1_2439
    );
  UUT_in_i2c_mux000063_SW0 : X_LUT4
    generic map(
      INIT => X"C8C0",
      LOC => "SLICE_X18Y52"
    )
    port map (
      ADR0 => UUT_N44,
      ADR1 => UUT_nstate_cmp_eq0007,
      ADR2 => UUT_in_i2c_cmp_eq0000,
      ADR3 => UUT_N38,
      O => N93
    );
  UUT_out_i2cclk_mux00001311 : X_LUT4
    generic map(
      INIT => X"F0A0",
      LOC => "SLICE_X20Y54"
    )
    port map (
      ADR0 => UUT_out_i2cclk_mux000050_0,
      ADR1 => VCC,
      ADR2 => CLK_sI2C_Clk_2470,
      ADR3 => UUT_out_i2cclk_mux000097_O,
      O => UUT_out_i2cclk_mux0000131
    );
  UUT_out_i2cclk : X_SFF
    generic map(
      LOC => "SLICE_X20Y54",
      INIT => '1'
    )
    port map (
      I => UUT_out_i2cclk_DXMUX_6418,
      CE => VCC,
      CLK => UUT_out_i2cclk_CLKINV_6401,
      SET => GND,
      RST => GND,
      SSET => UUT_out_i2cclk_SRINV_6402,
      SRST => GND,
      O => UUT_out_i2cclk_2438
    );
  UUT_delay_count_mux0000_11_11 : X_LUT4
    generic map(
      INIT => X"BABA",
      LOC => "SLICE_X25Y20"
    )
    port map (
      ADR0 => UUT_delay_count_or0000,
      ADR1 => UUT_ClkFallingEdge_2553,
      ADR2 => UUT_N107,
      ADR3 => VCC,
      O => UUT_N17
    );
  UUT_nstate_FFd4_In851 : X_LUT4
    generic map(
      INIT => X"FFA8",
      LOC => "SLICE_X24Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd4_In59_0,
      ADR2 => UUT_nstate_FFd4_In62_2521,
      ADR3 => UUT_nstate_FFd4_In28_O,
      O => UUT_nstate_FFd4_In85
    );
  UUT_nstate_FFd4 : X_SFF
    generic map(
      LOC => "SLICE_X24Y40",
      INIT => '0'
    )
    port map (
      I => UUT_nstate_FFd4_DXMUX_6475,
      CE => VCC,
      CLK => UUT_nstate_FFd4_CLKINV_6459,
      SET => GND,
      RST => GND,
      SSET => UUT_nstate_FFd4_SRINV_6460,
      SRST => GND,
      O => UUT_nstate_FFd4_2442
    );
  UUT_in_i2c_mux000034 : X_LUT4
    generic map(
      INIT => X"2000",
      LOC => "SLICE_X20Y52"
    )
    port map (
      ADR0 => UUT_N40,
      ADR1 => N113_0,
      ADR2 => UUT_N101,
      ADR3 => UUT_in_i2c_mux000032_O,
      O => UUT_in_i2c_mux000034_6501
    );
  UUT_writeCount_9 : X_FF
    generic map(
      LOC => "SLICE_X16Y4",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_9_DXMUX_5717,
      CE => VCC,
      CLK => UUT_writeCount_9_CLKINV_5702,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(9)
    );
  UUT_shiftReg_mux0000_3_14 : X_LUT4
    generic map(
      INIT => X"FEEE",
      LOC => "SLICE_X23Y34"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0006_0,
      ADR1 => UUT_shiftReg_mux0000_3_2_0,
      ADR2 => UUT_N46,
      ADR3 => UUT_shiftReg_mux0000_3_8_0,
      O => UUT_shiftReg_mux0000_3_14_5742
    );
  UUT_Dir_mux00012 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X25Y24"
    )
    port map (
      ADR0 => UUT_delay_count(6),
      ADR1 => UUT_delay_count(7),
      ADR2 => UUT_Dir_mux00012_SW0_O,
      ADR3 => UUT_delay_count(9),
      O => UUT_shiftReg_cmp_eq0002
    );
  UUT_ack_count_mux0000_0_971 : X_LUT4
    generic map(
      INIT => X"FCF0",
      LOC => "SLICE_X16Y53"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_N21_0,
      ADR2 => UUT_ack_count_mux0000_0_68_O,
      ADR3 => UUT_ack_count_share0000(0),
      O => UUT_ack_count_mux0000_0_97
    );
  UUT_ack_count_0 : X_SFF
    generic map(
      LOC => "SLICE_X16Y53",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_0_DXMUX_5797,
      CE => VCC,
      CLK => UUT_ack_count_0_CLKINV_5780,
      SET => GND,
      RST => GND,
      SSET => UUT_ack_count_0_SRINV_5781,
      SRST => GND,
      O => UUT_ack_count(0)
    );
  UUT_ack_count_mux0000_10_210 : X_LUT4
    generic map(
      INIT => X"0800",
      LOC => "SLICE_X17Y53"
    )
    port map (
      ADR0 => UUT_N38,
      ADR1 => UUT_ack_count_and0023,
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_nstate_cmp_eq0015,
      O => UUT_ack_count_mux0000_10_210_5823
    );
  UUT_ack_count_mux0000_10_231 : X_LUT4
    generic map(
      INIT => X"33FB",
      LOC => "SLICE_X17Y52"
    )
    port map (
      ADR0 => UUT_ack_count_mux0000_10_210_0,
      ADR1 => UUT_nstate_FFd3_In1_0,
      ADR2 => UUT_ack_count_mux0000_10_20_O,
      ADR3 => UUT_ClkRisingEdge_2447,
      O => UUT_N16
    );
  UUT_counter_mux0000_4_20 : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X19Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => N97_0,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_N40,
      O => UUT_counter_mux0000_4_20_5871
    );
  UUT_shiftReg_or000017 : X_LUT4
    generic map(
      INIT => X"FF7F",
      LOC => "SLICE_X26Y24"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => UUT_delay_count(1),
      ADR2 => UUT_delay_count(4),
      ADR3 => UUT_shiftReg_or000012_O,
      O => UUT_shiftReg_or000017_5895
    );
  UUT_pstate_mux0000_7_11104_SW0 : X_LUT4
    generic map(
      INIT => X"ABFB",
      LOC => "SLICE_X26Y39"
    )
    port map (
      ADR0 => UUT_pstate_mux0000_7_SW1_O,
      ADR1 => N54,
      ADR2 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR3 => N53,
      O => N58
    );
  UUT_out_i2cclk_mux0000258 : X_LUT4
    generic map(
      INIT => X"1505",
      LOC => "SLICE_X19Y56"
    )
    port map (
      ADR0 => UUT_ack_count(7),
      ADR1 => UUT_ack_count(5),
      ADR2 => UUT_out_i2cclk_mux0000258_SW0_O,
      ADR3 => UUT_ack_count(4),
      O => UUT_out_i2cclk_mux0000258_6135
    );
  UUT_shiftReg_mux0000_5_111 : X_LUT4
    generic map(
      INIT => X"FE10",
      LOC => "SLICE_X23Y29"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_232_0,
      ADR1 => UUT_shiftReg_mux0000_0_215_2583,
      ADR2 => N67_0,
      ADR3 => UUT_shiftReg_mux0000_0_257_SW3_O,
      O => UUT_shiftReg_mux0000_5_11
    );
  UUT_shiftReg_5 : X_SFF
    generic map(
      LOC => "SLICE_X23Y29",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_5_DXMUX_6166,
      CE => VCC,
      CLK => UUT_shiftReg_5_CLKINV_6150,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_5_SRINV_6151,
      SRST => GND,
      O => UUT_shiftReg(5)
    );
  UUT_writeCount_mux0000_0_SW1 : X_LUT4
    generic map(
      INIT => X"FD88",
      LOC => "SLICE_X21Y8"
    )
    port map (
      ADR0 => UUT_ClkFallingEdge_2553,
      ADR1 => UUT_writeCount_share0000(0),
      ADR2 => UUT_delay_count_or0000,
      ADR3 => UUT_writeCount(0),
      O => N19
    );
  UUT_nstate_cmp_eq0001 : X_LUT4
    generic map(
      INIT => X"0020",
      LOC => "SLICE_X23Y52"
    )
    port map (
      ADR0 => UUT_N112_0,
      ADR1 => UUT_ack_count(11),
      ADR2 => UUT_in_i2c_cmp_eq0000,
      ADR3 => N45_0,
      O => UUT_nstate_cmp_eq0001_6216
    );
  UUT_shiftReg_mux0000_7_101 : X_LUT4
    generic map(
      INIT => X"F0E4",
      LOC => "SLICE_X23Y28"
    )
    port map (
      ADR0 => UUT_shiftReg_mux0000_0_232_0,
      ADR1 => N64_0,
      ADR2 => UUT_shiftReg_mux0000_0_257_SW1_O,
      ADR3 => UUT_shiftReg_mux0000_0_215_2583,
      O => UUT_shiftReg_mux0000_7_10
    );
  UUT_shiftReg_7 : X_SFF
    generic map(
      LOC => "SLICE_X23Y28",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_7_DXMUX_6247,
      CE => VCC,
      CLK => UUT_shiftReg_7_CLKINV_6230,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_7_SRINV_6231,
      SRST => GND,
      O => UUT_shiftReg(7)
    );
  UUT_shiftReg_mux0000_2_1 : X_LUT4
    generic map(
      INIT => X"FF88",
      LOC => "SLICE_X23Y33"
    )
    port map (
      ADR0 => UUT_shiftReg(2),
      ADR1 => UUT_N15_0,
      ADR2 => VCC,
      ADR3 => UUT_shiftReg_mux0000_2_SW0_O,
      O => UUT_shiftReg_mux0000_2_1_6277
    );
  UUT_shiftReg_2 : X_SFF
    generic map(
      LOC => "SLICE_X23Y33",
      INIT => '0'
    )
    port map (
      I => UUT_shiftReg_2_DXMUX_6280,
      CE => VCC,
      CLK => UUT_shiftReg_2_CLKINV_6263,
      SET => GND,
      RST => GND,
      SSET => UUT_shiftReg_2_SRINV_6264,
      SRST => GND,
      O => UUT_shiftReg(2)
    );
  UUT_delay_count_mux0000_0_125 : X_LUT4
    generic map(
      INIT => X"7CFC",
      LOC => "SLICE_X29Y21"
    )
    port map (
      ADR0 => UUT_delay_count(6),
      ADR1 => UUT_delay_count(10),
      ADR2 => UUT_delay_count(2),
      ADR3 => UUT_delay_count_mux0000_0_125_SW0_O,
      O => UUT_delay_count_mux0000_0_125_6525
    );
  UUT_in_i2c_mux000037 : X_LUT4
    generic map(
      INIT => X"2020",
      LOC => "SLICE_X20Y53"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(1),
      ADR2 => UUT_N101,
      ADR3 => VCC,
      O => UUT_N41
    );
  UUT_in_i2c_mux000063 : X_LUT4
    generic map(
      INIT => X"FFEC",
      LOC => "SLICE_X19Y53"
    )
    port map (
      ADR0 => N93_0,
      ADR1 => UUT_in_i2c_mux000034_0,
      ADR2 => UUT_in_i2c_and0000_0,
      ADR3 => UUT_in_i2c_mux0000211_O,
      O => UUT_in_i2c_mux000063_6573
    );
  UUT_in_i2c_mux0000144 : X_LUT4
    generic map(
      INIT => X"AA2A",
      LOC => "SLICE_X20Y50"
    )
    port map (
      ADR0 => UUT_ack_count(8),
      ADR1 => UUT_ack_count(0),
      ADR2 => UUT_ack_count(4),
      ADR3 => UUT_in_i2c_mux0000131_O,
      O => UUT_in_i2c_mux0000144_6597
    );
  UUT_delay_count_mux0000_0_170 : X_LUT4
    generic map(
      INIT => X"F222",
      LOC => "SLICE_X27Y21"
    )
    port map (
      ADR0 => UUT_nstate_cmp_eq0014,
      ADR1 => UUT_Mcompar_delay_count_cmp_lt0000_cy_6_Q,
      ADR2 => UUT_delay_count_or0001,
      ADR3 => UUT_delay_count_mux0000_0_145_O,
      O => UUT_N3
    );
  UUT_in_i2c_mux000093 : X_LUT4
    generic map(
      INIT => X"CD45",
      LOC => "SLICE_X21Y49"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd1_2439,
      ADR2 => UUT_nstate_FFd2_2441,
      ADR3 => UUT_Dir_mux000035_2544,
      O => UUT_in_i2c_mux000093_6645
    );
  UUT_in_i2c_mux0000190 : X_LUT4
    generic map(
      INIT => X"F0E0",
      LOC => "SLICE_X21Y51"
    )
    port map (
      ADR0 => UUT_in_i2c_mux0000144_0,
      ADR1 => UUT_in_i2c_mux0000158_0,
      ADR2 => UUT_counter_mux0000_4_7_0,
      ADR3 => UUT_in_i2c_mux0000122_O,
      O => UUT_in_i2c_mux0000190_6669
    );
  UUT_in_i2c_mux0000275 : X_LUT4
    generic map(
      INIT => X"8F88",
      LOC => "SLICE_X24Y32"
    )
    port map (
      ADR0 => UUT_N29_0,
      ADR1 => UUT_shiftReg(0),
      ADR2 => UUT_shiftReg_cmp_eq0001,
      ADR3 => UUT_in_i2c_mux0000266_O,
      O => UUT_in_i2c_mux0000275_6693
    );
  UUT_delay_count_1 : X_FF
    generic map(
      LOC => "SLICE_X28Y20",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_1_DYMUX_7300,
      CE => VCC,
      CLK => UUT_delay_count_1_CLKINV_7292,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(1)
    );
  UUT_shiftReg_or000032 : X_LUT4
    generic map(
      INIT => X"5544",
      LOC => "SLICE_X28Y20"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => UUT_delay_count(1),
      ADR2 => VCC,
      ADR3 => UUT_delay_count(0),
      O => UUT_shiftReg_or000032_7309
    );
  UUT_delay_count_2 : X_FF
    generic map(
      LOC => "SLICE_X32Y17",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_3_DYMUX_7331,
      CE => VCC,
      CLK => UUT_delay_count_3_CLKINV_7323,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(2)
    );
  UUT_delay_count_mux0000_3_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X32Y17"
    )
    port map (
      ADR0 => UUT_N17_0,
      ADR1 => UUT_N3_0,
      ADR2 => UUT_delay_count_share0000(3),
      ADR3 => UUT_delay_count(3),
      O => UUT_delay_count_mux0000(3)
    );
  UUT_delay_count_3 : X_FF
    generic map(
      LOC => "SLICE_X32Y17",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_3_DXMUX_7342,
      CE => VCC,
      CLK => UUT_delay_count_3_CLKINV_7323,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(3)
    );
  UUT_delay_count_4 : X_FF
    generic map(
      LOC => "SLICE_X32Y16",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_5_DYMUX_7365,
      CE => VCC,
      CLK => UUT_delay_count_5_CLKINV_7357,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(4)
    );
  UUT_delay_count_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X32Y16"
    )
    port map (
      ADR0 => UUT_N3_0,
      ADR1 => UUT_N17_0,
      ADR2 => UUT_delay_count(5),
      ADR3 => UUT_delay_count_share0000(5),
      O => UUT_delay_count_mux0000(5)
    );
  UUT_delay_count_5 : X_FF
    generic map(
      LOC => "SLICE_X32Y16",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_5_DXMUX_7376,
      CE => VCC,
      CLK => UUT_delay_count_5_CLKINV_7357,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(5)
    );
  UUT_delay_count_6 : X_FF
    generic map(
      LOC => "SLICE_X32Y18",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_7_DYMUX_7399,
      CE => VCC,
      CLK => UUT_delay_count_7_CLKINV_7391,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(6)
    );
  UUT_delay_count_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X32Y18"
    )
    port map (
      ADR0 => UUT_delay_count(7),
      ADR1 => UUT_delay_count_share0000(7),
      ADR2 => UUT_N3_0,
      ADR3 => UUT_delay_count_or0000,
      O => UUT_delay_count_mux0000(7)
    );
  UUT_delay_count_7 : X_FF
    generic map(
      LOC => "SLICE_X32Y18",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_7_DXMUX_7410,
      CE => VCC,
      CLK => UUT_delay_count_7_CLKINV_7391,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(7)
    );
  UUT_delay_count_8 : X_FF
    generic map(
      LOC => "SLICE_X32Y19",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_9_DYMUX_7433,
      CE => VCC,
      CLK => UUT_delay_count_9_CLKINV_7425,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(8)
    );
  UUT_delay_count_mux0000_9_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X32Y19"
    )
    port map (
      ADR0 => UUT_delay_count_share0000(9),
      ADR1 => UUT_N3_0,
      ADR2 => UUT_delay_count(9),
      ADR3 => UUT_delay_count_or0000,
      O => UUT_delay_count_mux0000(9)
    );
  UUT_delay_count_9 : X_FF
    generic map(
      LOC => "SLICE_X32Y19",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_9_DXMUX_7444,
      CE => VCC,
      CLK => UUT_delay_count_9_CLKINV_7425,
      SET => GND,
      RST => GND,
      O => UUT_delay_count(9)
    );
  UUT_ack_count_10 : X_FF
    generic map(
      LOC => "SLICE_X16Y61",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_11_DYMUX_7467,
      CE => VCC,
      CLK => UUT_ack_count_11_CLKINV_7459,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(10)
    );
  UUT_ack_count_mux0000_11_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y61"
    )
    port map (
      ADR0 => UUT_ack_count_share0000(11),
      ADR1 => UUT_N16_0,
      ADR2 => UUT_ack_count(11),
      ADR3 => UUT_N21_0,
      O => UUT_ack_count_mux0000(11)
    );
  UUT_ack_count_11 : X_FF
    generic map(
      LOC => "SLICE_X16Y61",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_11_DXMUX_7478,
      CE => VCC,
      CLK => UUT_ack_count_11_CLKINV_7459,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(11)
    );
  UUT_ack_count_1 : X_FF
    generic map(
      LOC => "SLICE_X18Y59",
      INIT => '0'
    )
    port map (
      I => UUT_ack_count_7_DYMUX_7501,
      CE => VCC,
      CLK => UUT_ack_count_7_CLKINV_7493,
      SET => GND,
      RST => GND,
      O => UUT_ack_count(1)
    );
  UUT_ack_count_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X18Y59"
    )
    port map (
      ADR0 => UUT_N16_0,
      ADR1 => UUT_ack_count_share0000(7),
      ADR2 => UUT_N21_0,
      ADR3 => UUT_ack_count(7),
      O => UUT_ack_count_mux0000(7)
    );
  UUT_writeCount_3 : X_FF
    generic map(
      LOC => "SLICE_X16Y0",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_3_DXMUX_7108,
      CE => VCC,
      CLK => UUT_writeCount_3_CLKINV_7089,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(3)
    );
  UUT_writeCount_4 : X_FF
    generic map(
      LOC => "SLICE_X16Y2",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_5_DYMUX_7131,
      CE => VCC,
      CLK => UUT_writeCount_5_CLKINV_7123,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(4)
    );
  UUT_writeCount_mux0000_5_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y2"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_writeCount_share0000(5),
      ADR2 => UUT_N11,
      ADR3 => UUT_writeCount(5),
      O => UUT_writeCount_mux0000(5)
    );
  UUT_writeCount_5 : X_FF
    generic map(
      LOC => "SLICE_X16Y2",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_5_DXMUX_7142,
      CE => VCC,
      CLK => UUT_writeCount_5_CLKINV_7123,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(5)
    );
  UUT_writeCount_6 : X_FF
    generic map(
      LOC => "SLICE_X16Y3",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_7_DYMUX_7165,
      CE => VCC,
      CLK => UUT_writeCount_7_CLKINV_7157,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(6)
    );
  UUT_writeCount_mux0000_7_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X16Y3"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(7),
      ADR1 => UUT_writeCount(7),
      ADR2 => UUT_N31,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(7)
    );
  UUT_writeCount_7 : X_FF
    generic map(
      LOC => "SLICE_X16Y3",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_7_DXMUX_7176,
      CE => VCC,
      CLK => UUT_writeCount_7_CLKINV_7157,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(7)
    );
  UUT_prevClk : X_FF
    generic map(
      LOC => "SLICE_X20Y39",
      INIT => '0'
    )
    port map (
      I => UUT_prevClk_DYMUX_7198,
      CE => VCC,
      CLK => UUT_prevClk_CLKINV_7189,
      SET => GND,
      RST => GND,
      O => UUT_prevClk_2652
    );
  UUT_ClkFallingEdge_not00011 : X_LUT4
    generic map(
      INIT => X"FFBB",
      LOC => "SLICE_X20Y39"
    )
    port map (
      ADR0 => UUT_ClkEdge(0),
      ADR1 => UUT_prevClk_2652,
      ADR2 => VCC,
      ADR3 => UUT_ClkEdge(1),
      O => UUT_ClkFallingEdge_not0001
    );
  UUT_ClkRisingEdge : X_SFF
    generic map(
      LOC => "SLICE_X21Y38",
      INIT => '0'
    )
    port map (
      I => UUT_ClkRisingEdge_DYMUX_7226,
      CE => VCC,
      CLK => UUT_ClkRisingEdge_CLKINV_7215,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => UUT_ClkRisingEdge_SRINV_7216,
      O => UUT_ClkRisingEdge_2447
    );
  UUT_pstate_2 : X_FF
    generic map(
      LOC => "SLICE_X27Y39",
      INIT => '0'
    )
    port map (
      I => UUT_pstate_2_DYMUX_7249,
      CE => VCC,
      CLK => UUT_pstate_2_CLKINV_7241,
      SET => GND,
      RST => GND,
      O => UUT_pstate(2)
    );
  UUT_nstate_FFd1_In14_SW0 : X_LUT4
    generic map(
      INIT => X"FEFE",
      LOC => "SLICE_X27Y39"
    )
    port map (
      ADR0 => UUT_pstate(2),
      ADR1 => UUT_pstate(3),
      ADR2 => UUT_pstate(4),
      ADR3 => VCC,
      O => N77
    );
  UUT_delay_count_0 : X_SFF
    generic map(
      LOC => "SLICE_X28Y15",
      INIT => '0'
    )
    port map (
      I => UUT_delay_count_0_DYMUX_7277,
      CE => VCC,
      CLK => UUT_delay_count_0_CLKINV_7266,
      SET => GND,
      RST => GND,
      SSET => UUT_delay_count_0_SRINV_7267,
      SRST => GND,
      O => UUT_delay_count(0)
    );
  UUT_writeCount_28 : X_FF
    generic map(
      LOC => "SLICE_X16Y15",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_29_DYMUX_7961,
      CE => VCC,
      CLK => UUT_writeCount_29_CLKINV_7953,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(28)
    );
  UUT_writeCount_mux0000_29_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y15"
    )
    port map (
      ADR0 => UUT_N11,
      ADR1 => UUT_writeCount_share0000(29),
      ADR2 => UUT_N31,
      ADR3 => UUT_writeCount(29),
      O => UUT_writeCount_mux0000(29)
    );
  UUT_writeCount_29 : X_FF
    generic map(
      LOC => "SLICE_X16Y15",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_29_DXMUX_7972,
      CE => VCC,
      CLK => UUT_writeCount_29_CLKINV_7953,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(29)
    );
  sSW_3_or00001 : X_LUT4
    generic map(
      INIT => X"FF77",
      LOC => "SLICE_X24Y54"
    )
    port map (
      ADR0 => sSW(0),
      ADR1 => sSW(1),
      ADR2 => VCC,
      ADR3 => sSW(2),
      O => sSW_3_or0000
    );
  sSW_0 : X_FF
    generic map(
      LOC => "SLICE_X24Y57",
      INIT => '0'
    )
    port map (
      I => sSW_1_DYMUX_8019,
      CE => VCC,
      CLK => sSW_1_CLKINV_8017,
      SET => GND,
      RST => GND,
      O => sSW(0)
    );
  sSW_1 : X_FF
    generic map(
      LOC => "SLICE_X24Y57",
      INIT => '0'
    )
    port map (
      I => sSW_1_DXMUX_8024,
      CE => VCC,
      CLK => sSW_1_CLKINV_8017,
      SET => GND,
      RST => GND,
      O => sSW(1)
    );
  UUT_shiftReg_cmp_eq000331_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X25Y23"
    )
    port map (
      ADR0 => UUT_delay_count(2),
      ADR1 => UUT_delay_count(5),
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_delay_count(0),
      O => N51
    );
  sSW_2 : X_SFF
    generic map(
      LOC => "SLICE_X24Y55",
      INIT => '0'
    )
    port map (
      I => sSW_2_DYMUX_8061,
      CE => sSW_2_CEINV_8057,
      CLK => sSW_2_CLKINV_8058,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => sSW_2_SRINV_8059,
      O => sSW(2)
    );
  sSW_3 : X_SFF
    generic map(
      LOC => "SLICE_X24Y47",
      INIT => '0'
    )
    port map (
      I => sSW_3_DYMUX_8074,
      CE => VCC,
      CLK => sSW_3_CLKINV_8071,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => sSW_3_SRINV_8072,
      O => sSW(3)
    );
  UUT_shiftReg_cmp_eq00032_SW1 : X_LUT4
    generic map(
      INIT => X"FFFE",
      LOC => "SLICE_X27Y24"
    )
    port map (
      ADR0 => UUT_delay_count(1),
      ADR1 => UUT_delay_count(7),
      ADR2 => UUT_delay_count(9),
      ADR3 => UUT_delay_count(0),
      O => N73
    );
  UUT_nstate_cmp_eq0000_SW0 : X_LUT4
    generic map(
      INIT => X"FCFC",
      LOC => "SLICE_X17Y40"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_counter(4),
      ADR2 => UUT_counter(1),
      ADR3 => VCC,
      O => N21
    );
  UUT_writeCount_14 : X_FF
    generic map(
      LOC => "SLICE_X16Y6",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_15_DYMUX_7739,
      CE => VCC,
      CLK => UUT_writeCount_15_CLKINV_7731,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(14)
    );
  UUT_writeCount_mux0000_15_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X16Y6"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(15),
      ADR1 => UUT_writeCount(15),
      ADR2 => UUT_N31,
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(15)
    );
  UUT_writeCount_15 : X_FF
    generic map(
      LOC => "SLICE_X16Y6",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_15_DXMUX_7750,
      CE => VCC,
      CLK => UUT_writeCount_15_CLKINV_7731,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(15)
    );
  UUT_writeCount_22 : X_FF
    generic map(
      LOC => "SLICE_X16Y11",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_23_DYMUX_7773,
      CE => VCC,
      CLK => UUT_writeCount_23_CLKINV_7765,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(22)
    );
  UUT_writeCount_mux0000_23_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y11"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(23),
      ADR1 => UUT_N31,
      ADR2 => UUT_writeCount(23),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(23)
    );
  UUT_writeCount_23 : X_FF
    generic map(
      LOC => "SLICE_X16Y11",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_23_DXMUX_7784,
      CE => VCC,
      CLK => UUT_writeCount_23_CLKINV_7765,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(23)
    );
  UUT_writeCount_30 : X_FF
    generic map(
      LOC => "SLICE_X16Y14",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_30_DYMUX_7802,
      CE => VCC,
      CLK => UUT_writeCount_30_CLKINV_7794,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(30)
    );
  UUT_writeCount_16 : X_FF
    generic map(
      LOC => "SLICE_X16Y8",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_17_DYMUX_7825,
      CE => VCC,
      CLK => UUT_writeCount_17_CLKINV_7817,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(16)
    );
  UUT_writeCount_mux0000_17_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y8"
    )
    port map (
      ADR0 => UUT_N31,
      ADR1 => UUT_writeCount_share0000(17),
      ADR2 => UUT_writeCount(17),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(17)
    );
  UUT_writeCount_17 : X_FF
    generic map(
      LOC => "SLICE_X16Y8",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_17_DXMUX_7836,
      CE => VCC,
      CLK => UUT_writeCount_17_CLKINV_7817,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(17)
    );
  UUT_writeCount_24 : X_FF
    generic map(
      LOC => "SLICE_X16Y13",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_25_DYMUX_7859,
      CE => VCC,
      CLK => UUT_writeCount_25_CLKINV_7851,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(24)
    );
  UUT_writeCount_mux0000_25_1 : X_LUT4
    generic map(
      INIT => X"ECA0",
      LOC => "SLICE_X16Y13"
    )
    port map (
      ADR0 => UUT_writeCount(25),
      ADR1 => UUT_writeCount_share0000(25),
      ADR2 => UUT_N11,
      ADR3 => UUT_N31,
      O => UUT_writeCount_mux0000(25)
    );
  UUT_writeCount_25 : X_FF
    generic map(
      LOC => "SLICE_X16Y13",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_25_DXMUX_7870,
      CE => VCC,
      CLK => UUT_writeCount_25_CLKINV_7851,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(25)
    );
  UUT_writeCount_18 : X_FF
    generic map(
      LOC => "SLICE_X16Y9",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_19_DYMUX_7893,
      CE => VCC,
      CLK => UUT_writeCount_19_CLKINV_7885,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(18)
    );
  UUT_writeCount_mux0000_19_1 : X_LUT4
    generic map(
      INIT => X"F888",
      LOC => "SLICE_X16Y9"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(19),
      ADR1 => UUT_N31,
      ADR2 => UUT_writeCount(19),
      ADR3 => UUT_N11,
      O => UUT_writeCount_mux0000(19)
    );
  UUT_writeCount_19 : X_FF
    generic map(
      LOC => "SLICE_X16Y9",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_19_DXMUX_7904,
      CE => VCC,
      CLK => UUT_writeCount_19_CLKINV_7885,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(19)
    );
  UUT_writeCount_26 : X_FF
    generic map(
      LOC => "SLICE_X16Y12",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_27_DYMUX_7927,
      CE => VCC,
      CLK => UUT_writeCount_27_CLKINV_7919,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(26)
    );
  UUT_writeCount_mux0000_27_1 : X_LUT4
    generic map(
      INIT => X"EAC0",
      LOC => "SLICE_X16Y12"
    )
    port map (
      ADR0 => UUT_writeCount_share0000(27),
      ADR1 => UUT_N11,
      ADR2 => UUT_writeCount(27),
      ADR3 => UUT_N31,
      O => UUT_writeCount_mux0000(27)
    );
  UUT_writeCount_27 : X_FF
    generic map(
      LOC => "SLICE_X16Y12",
      INIT => '0'
    )
    port map (
      I => UUT_writeCount_27_DXMUX_7938,
      CE => VCC,
      CLK => UUT_writeCount_27_CLKINV_7919,
      SET => GND,
      RST => GND,
      O => UUT_writeCount(27)
    );
  UUT_pstate_mux0000_7_SW0 : X_LUT4
    generic map(
      INIT => X"1000",
      LOC => "SLICE_X31Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => UUT_nstate_FFd3_2440,
      O => N33
    );
  UUT_pstate_mux0000_6_SW1 : X_LUT4
    generic map(
      INIT => X"775F",
      LOC => "SLICE_X27Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_7_Q,
      ADR2 => UUT_nstate_FFd2_2441,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N37
    );
  UUT_counter_mux0000_4_471 : X_LUT4
    generic map(
      INIT => X"E4A0",
      LOC => "SLICE_X16Y41"
    )
    port map (
      ADR0 => UUT_counter(0),
      ADR1 => UUT_ClkRisingEdge_2447,
      ADR2 => UUT_N62,
      ADR3 => UUT_nstate_cmp_eq0012_0,
      O => UUT_counter_mux0000_4_47
    );
  UUT_counter_0 : X_SFF
    generic map(
      LOC => "SLICE_X16Y41",
      INIT => '0'
    )
    port map (
      I => UUT_counter_0_DXMUX_8735,
      CE => VCC,
      CLK => UUT_counter_0_CLKINV_8718,
      SET => GND,
      RST => GND,
      SSET => UUT_counter_0_SRINV_8719,
      SRST => GND,
      O => UUT_counter(0)
    );
  UUT_nstate_FFd4_In41 : X_LUT4
    generic map(
      INIT => X"0010",
      LOC => "SLICE_X25Y40"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_N106
    );
  UUT_nstate_FFd3_In14 : X_LUT4
    generic map(
      INIT => X"CCC8",
      LOC => "SLICE_X24Y41"
    )
    port map (
      ADR0 => UUT_nstate_FFd4_2442,
      ADR1 => UUT_nstate_FFd3_2440,
      ADR2 => N128,
      ADR3 => UUT_Mcompar_nstate_cmp_gt0002_cy_5_Q,
      O => UUT_nstate_FFd3_In14_8785
    );
  UUT_nstate_FFd2_In27 : X_LUT4
    generic map(
      INIT => X"F0E0",
      LOC => "SLICE_X21Y53"
    )
    port map (
      ADR0 => UUT_N32_0,
      ADR1 => UUT_N66_0,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd2_In11_2670,
      O => UUT_nstate_FFd2_In27_8821
    );
  UUT_nstate_cmp_eq00051 : X_LUT4
    generic map(
      INIT => X"00A0",
      LOC => "SLICE_X21Y50"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => VCC,
      ADR2 => UUT_N41_0,
      ADR3 => UUT_N32_0,
      O => UUT_nstate_cmp_eq0005
    );
  UUT_shiftReg_mux0000_6_11_SW0 : X_LUT4
    generic map(
      INIT => X"0080",
      LOC => "SLICE_X23Y31"
    )
    port map (
      ADR0 => UUT_shiftReg(5),
      ADR1 => UUT_ClkRisingEdge_2447,
      ADR2 => UUT_nstate_FFd1_2439,
      ADR3 => UUT_nstate_FFd4_2442,
      O => N101
    );
  UUT_ack_count_or000411 : X_LUT4
    generic map(
      INIT => X"77FF",
      LOC => "SLICE_X14Y54"
    )
    port map (
      ADR0 => UUT_ack_count(5),
      ADR1 => UUT_ack_count(3),
      ADR2 => VCC,
      ADR3 => UUT_ack_count(0),
      O => UUT_N66
    );
  UUT_out_i2cclk_mux0000210 : X_LUT4
    generic map(
      INIT => X"D4D4",
      LOC => "SLICE_X18Y55"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => UUT_ack_count(6),
      ADR2 => UUT_ack_count(5),
      ADR3 => VCC,
      O => UUT_out_i2cclk_mux0000210_8220
    );
  UUT_in_i2c_mux000072 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X24Y50"
    )
    port map (
      ADR0 => UUT_ack_count(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(8),
      O => UUT_N112
    );
  UUT_shiftReg_cmp_eq000331 : X_LUT4
    generic map(
      INIT => X"0100",
      LOC => "SLICE_X25Y26"
    )
    port map (
      ADR0 => UUT_delay_count(0),
      ADR1 => UUT_delay_count(5),
      ADR2 => UUT_delay_count(1),
      ADR3 => UUT_N33_0,
      O => UUT_delay_count_and0000
    );
  UUT_N21130_SW0 : X_LUT4
    generic map(
      INIT => X"8000",
      LOC => "SLICE_X21Y54"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_ack_count(4),
      ADR2 => UUT_ack_count(0),
      ADR3 => UUT_ack_count(1),
      O => N91
    );
  UUT_shiftReg_mux0000_6_5 : X_LUT4
    generic map(
      INIT => X"0808",
      LOC => "SLICE_X22Y38"
    )
    port map (
      ADR0 => UUT_nstate_FFd3_2440,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => UUT_nstate_FFd4_2442,
      ADR3 => VCC,
      O => UUT_shiftReg_mux0000_3_8
    );
  UUT_counter_mux0000_4_2_SW1 : X_LUT4
    generic map(
      INIT => X"44EE",
      LOC => "SLICE_X17Y51"
    )
    port map (
      ADR0 => UUT_nstate_FFd1_2439,
      ADR1 => UUT_nstate_FFd2_2441,
      ADR2 => VCC,
      ADR3 => UUT_ClkRisingEdge_2447,
      O => N120
    );
  UUT_shiftReg_mux0000_0_9 : X_LUT4
    generic map(
      INIT => X"FFF8",
      LOC => "SLICE_X22Y36"
    )
    port map (
      ADR0 => UUT_N46,
      ADR1 => UUT_N0,
      ADR2 => UUT_nstate_cmp_eq0006_0,
      ADR3 => UUT_shiftReg_mux0000_0_2,
      O => UUT_shiftReg_mux0000_0_9_8536
    );
  UUT_shiftReg_mux0000_7_5 : X_LUT4
    generic map(
      INIT => X"EAAA",
      LOC => "SLICE_X22Y31"
    )
    port map (
      ADR0 => N99_0,
      ADR1 => UUT_N0,
      ADR2 => UUT_shiftReg_and0000_0,
      ADR3 => UUT_shiftReg_cmp_eq0002_0,
      O => UUT_shiftReg_mux0000_7_5_8560
    );
  UUT_writeCount_mux0000_0_SW0 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X24Y15"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count_or0000,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(0),
      O => N18
    );
  UUT_nstate_Out01 : X_LUT4
    generic map(
      INIT => X"0005",
      LOC => "SLICE_X20Y51"
    )
    port map (
      ADR0 => UUT_nstate_FFd2_2441,
      ADR1 => VCC,
      ADR2 => UUT_nstate_FFd3_2440,
      ADR3 => UUT_nstate_FFd4_2442,
      O => UUT_nstate_cmp_eq0006
    );
  UUT_in_i2c_mux0000158 : X_LUT4
    generic map(
      INIT => X"00FE",
      LOC => "SLICE_X18Y50"
    )
    port map (
      ADR0 => UUT_ack_count(2),
      ADR1 => UUT_in_i2c_mux000078,
      ADR2 => UUT_ack_count(6),
      ADR3 => UUT_ack_count(8),
      O => UUT_in_i2c_mux0000158_8632
    );
  UUT_ClkFallingEdge : X_SFF
    generic map(
      LOC => "SLICE_X21Y39",
      INIT => '0'
    )
    port map (
      I => UUT_ClkFallingEdge_DYMUX_8642,
      CE => VCC,
      CLK => UUT_ClkFallingEdge_CLKINV_8639,
      SET => GND,
      RST => GND,
      SSET => GND,
      SRST => UUT_ClkFallingEdge_SRINV_8640,
      O => UUT_ClkFallingEdge_2553
    );
  GLOBAL_LOGIC0_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  UUT_writeCount_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y0"
    )
    port map (
      ADR0 => UUT_writeCount(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_0_G
    );
  UUT_writeCount_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_2_F
    );
  UUT_writeCount_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y1"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(3),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_2_G
    );
  UUT_writeCount_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y2"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_4_F
    );
  UUT_writeCount_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y2"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(5),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_4_G
    );
  UUT_writeCount_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(6),
      O => UUT_writeCount_share0000_6_F
    );
  UUT_writeCount_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(7),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_6_G
    );
  UUT_writeCount_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y4"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(8),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_8_F
    );
  UUT_writeCount_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y4"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(9),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_8_G
    );
  UUT_writeCount_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y5"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_10_F
    );
  UUT_writeCount_share0000_10_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y5"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(11),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_10_G
    );
  UUT_ack_count_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y60"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(8),
      ADR3 => VCC,
      O => UUT_ack_count_share0000_8_F
    );
  UUT_ack_count_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y60"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_ack_count(9),
      ADR3 => VCC,
      O => UUT_ack_count_share0000_8_G
    );
  UUT_ack_count_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y61"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(10),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_10_F
    );
  UUT_delay_count_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X33Y15"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(1),
      ADR3 => VCC,
      O => UUT_delay_count_share0000_0_G
    );
  UUT_delay_count_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X33Y16"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(2),
      ADR3 => VCC,
      O => UUT_delay_count_share0000_2_F
    );
  UUT_delay_count_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X33Y16"
    )
    port map (
      ADR0 => UUT_delay_count(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_2_G
    );
  UUT_writeCount_share0000_28_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y14"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(28),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_28_F
    );
  UUT_writeCount_share0000_28_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y14"
    )
    port map (
      ADR0 => UUT_writeCount(29),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_28_G
    );
  UUT_ack_count_share0000_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y56"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(1),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_0_G
    );
  UUT_ack_count_share0000_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y57"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(2),
      O => UUT_ack_count_share0000_2_F
    );
  UUT_ack_count_share0000_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y57"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_ack_count(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_2_G
    );
  UUT_ack_count_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y58"
    )
    port map (
      ADR0 => UUT_ack_count(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_4_F
    );
  UUT_ack_count_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y58"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(5),
      O => UUT_ack_count_share0000_4_G
    );
  UUT_ack_count_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y59"
    )
    port map (
      ADR0 => UUT_ack_count(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_ack_count_share0000_6_F
    );
  UUT_ack_count_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y59"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_ack_count(7),
      O => UUT_ack_count_share0000_6_G
    );
  UUT_writeCount_share0000_12_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y6"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(12),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_12_F
    );
  UUT_writeCount_share0000_12_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y6"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(13),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_12_G
    );
  UUT_writeCount_share0000_14_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y7"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(14),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_14_F
    );
  UUT_writeCount_share0000_14_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y7"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(15),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_14_G
    );
  UUT_writeCount_share0000_16_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y8"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(16),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_16_F
    );
  UUT_writeCount_share0000_16_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y8"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(17),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_16_G
    );
  UUT_writeCount_share0000_18_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y9"
    )
    port map (
      ADR0 => UUT_writeCount(18),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_18_F
    );
  UUT_writeCount_share0000_18_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y9"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(19),
      O => UUT_writeCount_share0000_18_G
    );
  UUT_writeCount_share0000_20_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y10"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(20),
      O => UUT_writeCount_share0000_20_F
    );
  UUT_writeCount_share0000_20_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y10"
    )
    port map (
      ADR0 => UUT_writeCount(21),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_20_G
    );
  UUT_writeCount_share0000_22_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y11"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(22),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_22_F
    );
  UUT_writeCount_share0000_22_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y11"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(23),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_22_G
    );
  UUT_writeCount_share0000_24_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X17Y12"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_writeCount(24),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_24_F
    );
  UUT_writeCount_share0000_24_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X17Y12"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_writeCount(25),
      ADR3 => VCC,
      O => UUT_writeCount_share0000_24_G
    );
  UUT_writeCount_share0000_26_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X17Y13"
    )
    port map (
      ADR0 => UUT_writeCount(26),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_writeCount_share0000_26_F
    );
  UUT_writeCount_share0000_26_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X17Y13"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_writeCount(27),
      O => UUT_writeCount_share0000_26_G
    );
  CLK_clk_div_2_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X29Y36"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => CLK_clk_div(2),
      ADR3 => VCC,
      O => CLK_clk_div_2_F
    );
  CLK_clk_div_2_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X29Y36"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CLK_clk_div(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_clk_div_2_G
    );
  CLK_clk_div_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X29Y37"
    )
    port map (
      ADR0 => CLK_clk_div(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_clk_div_4_F
    );
  CLK_clk_div_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X29Y37"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => CLK_clk_div(5),
      O => CLK_clk_div_4_G
    );
  CLK_clk_div_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X29Y38"
    )
    port map (
      ADR0 => CLK_clk_div(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CLK_clk_div_6_F
    );
  UUT_delay_count_share0000_4_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y17"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(4),
      O => UUT_delay_count_share0000_4_F
    );
  UUT_delay_count_share0000_4_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y17"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(5),
      O => UUT_delay_count_share0000_4_G
    );
  UUT_delay_count_share0000_6_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X33Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(6),
      ADR3 => VCC,
      O => UUT_delay_count_share0000_6_F
    );
  UUT_delay_count_share0000_6_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(7),
      O => UUT_delay_count_share0000_6_G
    );
  UUT_delay_count_share0000_8_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y19"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(8),
      O => UUT_delay_count_share0000_8_F
    );
  UUT_delay_count_share0000_8_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X33Y19"
    )
    port map (
      ADR0 => UUT_delay_count(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_8_G
    );
  UUT_delay_count_share0000_10_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"AAAA",
      LOC => "SLICE_X33Y20"
    )
    port map (
      ADR0 => UUT_delay_count(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_10_F
    );
  UUT_delay_count_share0000_10_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"CCCC",
      LOC => "SLICE_X33Y20"
    )
    port map (
      ADR0 => VCC,
      ADR1 => UUT_delay_count(11),
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_delay_count_share0000_10_G
    );
  UUT_delay_count_share0000_12_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"F0F0",
      LOC => "SLICE_X33Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => UUT_delay_count(12),
      ADR3 => VCC,
      O => UUT_delay_count_share0000_12_F
    );
  UUT_delay_count_share0000_12_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y21"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(13),
      O => UUT_delay_count_share0000_12_G
    );
  UUT_delay_count_share0000_14_F_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X33Y22"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => UUT_delay_count(14),
      O => UUT_delay_count_share0000_14_F
    );
  CLK_clk_div_0_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"FF00",
      LOC => "SLICE_X29Y35"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => CLK_clk_div(1),
      O => CLK_clk_div_0_G
    );
  I2C_Data_OUTPUT_TFF_TMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_Dir_2431,
      O => I2C_Data_T
    );
  I2C_Data_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_in_i2c_2430,
      O => I2C_Data_O
    );
  I2C_Clk_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD18",
      PATHPULSE => 798 ps
    )
    port map (
      I => UUT_out_i2cclk_2438,
      O => I2C_Clk_O
    );
  UUT_nstate_FFd3_G_X_LUT4 : X_LUT4
    generic map(
      INIT => X"0000",
      LOC => "SLICE_X25Y41"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => UUT_nstate_FFd3_G
    );
  NlwBlock_I2CmasterDemo2_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_I2CmasterDemo2_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

